Lines Matching +full:0 +full:x900000

13 #define NORTH	0x500000
14 #define WEST	0x100000
15 #define EAST	0x900000
42 		.ctl_reg = base + 0x1000 * id,	\
43 		.io_reg = base + 0x4 + 0x1000 * id,		\
44 		.intr_cfg_reg = base + 0x8 + 0x1000 * id,	\
45 		.intr_status_reg = base + 0xc + 0x1000 * id,	\
46 		.intr_target_reg = base + 0x8 + 0x1000 * id,	\
48 		.pull_bit = 0,			\
51 		.in_bit = 0,			\
53 		.intr_enable_bit = 0,		\
54 		.intr_status_bit = 0,		\
69 		.io_reg = 0,				\
70 		.intr_cfg_reg = 0,			\
71 		.intr_status_reg = 0,			\
72 		.intr_target_reg = 0,			\
94 		.io_reg = offset + 0x4,			\
95 		.intr_cfg_reg = 0,			\
96 		.intr_status_reg = 0,			\
97 		.intr_target_reg = 0,			\
100 		.drv_bit = 0,				\
103 		.out_bit = 0,				\
114 	PINCTRL_PIN(0, "GPIO_0"),
272 DECLARE_MSM_GPIO_PINS(0);
1350 	PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1500 	SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
1501 	SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
1502 	SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
1503 	UFS_RESET(ufs_reset, 0x19d000),