Lines Matching full:pctrl
41 * @pctrl: pinctrl handle.
60 struct pinctrl_dev *pctrl; member
82 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
85 return readl(pctrl->regs[g->tile] + g->name##_reg); \
87 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
90 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
101 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in MSM_ACCESSOR() local
103 return pctrl->soc->ngroups; in MSM_ACCESSOR()
109 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
111 return pctrl->soc->groups[group].name; in msm_get_group_name()
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
121 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
122 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
136 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
137 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
144 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
146 return pctrl->soc->nfunctions; in msm_get_functions_count()
152 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
154 return pctrl->soc->functions[function].name; in msm_get_function_name()
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
164 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
165 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
173 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
179 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
190 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
192 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
195 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
197 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
206 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
207 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
226 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
276 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
284 g = &pctrl->soc->groups[group]; in msm_config_group_get()
286 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
290 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
306 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
314 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
335 val = msm_readl_io(pctrl, g); in msm_config_group_get()
359 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
369 g = &pctrl->soc->groups[group]; in msm_config_group_set()
375 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
388 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
394 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
411 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
412 val = msm_readl_io(pctrl, g); in msm_config_group_set()
417 msm_writel_io(val, pctrl, g); in msm_config_group_set()
418 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
428 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
435 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
439 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
440 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
443 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
444 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
459 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
463 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
465 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
467 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
469 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
471 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
479 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
483 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
485 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
487 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
492 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
494 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
496 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
498 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
505 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
509 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
511 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
520 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
523 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
525 val = msm_readl_io(pctrl, g); in msm_gpio_get()
532 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
536 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
538 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
540 val = msm_readl_io(pctrl, g); in msm_gpio_set()
545 msm_writel_io(val, pctrl, g); in msm_gpio_set()
547 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
560 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
584 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
585 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
586 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
601 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
625 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
628 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
636 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
646 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
657 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
659 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
703 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
712 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
714 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
716 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
718 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
719 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
723 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
730 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
738 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
741 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
743 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
745 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
770 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
772 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
774 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
780 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_clear_unmask() local
788 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_clear_unmask()
791 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_clear_unmask()
793 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_clear_unmask()
801 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_clear_unmask()
803 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_clear_unmask()
806 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_clear_unmask()
809 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_clear_unmask()
811 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_clear_unmask()
813 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_clear_unmask()
819 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_enable() local
824 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
831 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_disable() local
836 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
857 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_update_dual_edge_parent() local
858 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
864 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
877 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
888 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
894 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
899 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
900 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
905 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
907 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
909 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_ack()
914 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_ack()
916 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
917 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
919 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
926 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_needs_dual_edge_parent_workaround() local
929 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
930 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
936 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
942 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
951 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
952 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
957 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
959 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
965 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
967 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
973 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
974 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
984 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
988 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
991 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
999 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1047 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1049 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1050 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1052 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1065 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
1073 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1076 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1082 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
1088 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1110 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_reqres()
1131 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_affinity() local
1133 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1142 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_vcpu_affinity() local
1144 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1154 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
1167 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1168 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1169 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1190 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_wakeirq() local
1197 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1198 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1208 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
1210 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1213 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1216 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1221 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1228 chip = &pctrl->chip; in msm_gpio_init()
1231 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1232 chip->parent = pctrl->dev; in msm_gpio_init()
1234 chip->of_node = pctrl->dev->of_node; in msm_gpio_init()
1235 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1238 pctrl->irq_chip.name = "msmgpio"; in msm_gpio_init()
1239 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; in msm_gpio_init()
1240 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; in msm_gpio_init()
1241 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; in msm_gpio_init()
1242 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; in msm_gpio_init()
1243 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; in msm_gpio_init()
1244 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; in msm_gpio_init()
1245 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; in msm_gpio_init()
1246 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; in msm_gpio_init()
1247 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; in msm_gpio_init()
1248 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; in msm_gpio_init()
1249 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; in msm_gpio_init()
1250 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND | in msm_gpio_init()
1254 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1262 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; in msm_gpio_init()
1268 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1269 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1270 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1275 girq->chip = &pctrl->irq_chip; in msm_gpio_init()
1277 girq->fwnode = pctrl->dev->fwnode; in msm_gpio_init()
1279 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1285 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1287 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1289 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1303 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1304 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1305 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1307 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1308 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1319 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); in msm_ps_hold_restart() local
1321 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1333 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1336 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1338 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1340 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1341 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1342 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1343 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1345 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1353 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1355 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1360 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1362 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1373 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1378 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1379 if (!pctrl) in msm_pinctrl_probe()
1382 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1383 pctrl->soc = soc_data; in msm_pinctrl_probe()
1384 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1385 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1386 pctrl->dev->of_node, in msm_pinctrl_probe()
1389 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1395 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1396 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1397 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1401 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1402 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1403 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1405 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1408 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1410 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1411 if (pctrl->irq < 0) in msm_pinctrl_probe()
1412 return pctrl->irq; in msm_pinctrl_probe()
1414 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1415 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1416 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1417 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1418 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1419 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1420 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1422 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1423 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1425 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1428 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1432 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()
1442 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); in msm_pinctrl_remove() local
1444 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1446 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()