Lines Matching +full:soc +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/soc/qcom/irq.h>
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
39 * struct msm_pinctrl - state for a pinctrl-msm device
54 * @soc: Reference to soc_data of platform specific data.
76 const struct msm_pinctrl_soc_data *soc; member
85 return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
103 return pctrl->soc->ngroups; in MSM_ACCESSOR()
111 return pctrl->soc->groups[group].name; in msm_get_group_name()
121 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
122 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
137 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
139 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
146 return pctrl->soc->nfunctions; in msm_get_functions_count()
154 return pctrl->soc->functions[function].name; in msm_get_function_name()
164 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
165 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
179 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
180 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
182 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
183 if (g->funcs[i] == function) in msm_pinmux_set_mux()
187 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
188 return -EINVAL; in msm_pinmux_set_mux()
190 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
194 val |= i << g->mux_bit; in msm_pinmux_set_mux()
197 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
207 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
210 if (!g->nfuncs) in msm_pinmux_request_gpio()
214 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); in msm_pinmux_request_gpio()
237 *bit = g->pull_bit; in msm_config_reg()
241 *bit = g->od_bit; in msm_config_reg()
245 *bit = g->drv_bit; in msm_config_reg()
250 *bit = g->oe_bit; in msm_config_reg()
254 return -ENOTSUPP; in msm_config_reg()
284 g = &pctrl->soc->groups[group]; in msm_config_group_get()
297 return -EINVAL; in msm_config_group_get()
302 return -EINVAL; in msm_config_group_get()
306 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
307 return -ENOTSUPP; in msm_config_group_get()
310 return -EINVAL; in msm_config_group_get()
314 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
319 return -EINVAL; in msm_config_group_get()
322 /* Pin is not open-drain */ in msm_config_group_get()
324 return -EINVAL; in msm_config_group_get()
333 return -EINVAL; in msm_config_group_get()
336 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
341 return -EINVAL; in msm_config_group_get()
345 return -ENOTSUPP; in msm_config_group_get()
369 g = &pctrl->soc->groups[group]; in msm_config_group_set()
388 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
389 return -ENOTSUPP; in msm_config_group_set()
394 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
405 arg = -1; in msm_config_group_set()
407 arg = (arg / 2) - 1; in msm_config_group_set()
411 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
414 val |= BIT(g->out_bit); in msm_config_group_set()
416 val &= ~BIT(g->out_bit); in msm_config_group_set()
418 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
428 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
430 return -EINVAL; in msm_config_group_set()
433 /* Range-check user-supplied value */ in msm_config_group_set()
435 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
436 return -EINVAL; in msm_config_group_set()
439 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
444 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
463 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
465 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
468 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
471 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
483 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
485 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
489 val |= BIT(g->out_bit); in msm_gpio_direction_output()
491 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
495 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
498 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
509 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
513 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
523 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
526 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
536 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
538 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
542 val |= BIT(g->out_bit); in msm_gpio_set()
544 val &= ~BIT(g->out_bit); in msm_gpio_set()
547 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
553 static void msm_gpio_dbg_show_one(struct seq_file *s, in msm_gpio_dbg_show_one() argument
584 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
588 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
589 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
590 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
591 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
594 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
596 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
598 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
599 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); in msm_gpio_dbg_show_one()
600 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); in msm_gpio_dbg_show_one()
601 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
602 seq_printf(s, " %s", pulls_no_keeper[pull]); in msm_gpio_dbg_show_one()
604 seq_printf(s, " %s", pulls_keeper[pull]); in msm_gpio_dbg_show_one()
605 seq_puts(s, "\n"); in msm_gpio_dbg_show_one()
608 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) in msm_gpio_dbg_show() argument
610 unsigned gpio = chip->base; in msm_gpio_dbg_show()
613 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
614 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); in msm_gpio_dbg_show()
628 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
636 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
637 return -EINVAL; in msm_gpio_init_valid_mask()
646 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
651 return -EINVAL; in msm_gpio_init_valid_mask()
655 return -ENOMEM; in msm_gpio_init_valid_mask()
657 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
659 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
683 /* For dual-edge interrupts in software, since some hardware has no
687 * settings of both-edge irq lines to try and catch the next edge.
690 * - the status bit goes high, indicating that an edge was caught, or
691 * - the input value of the gpio doesn't change during the attempt.
696 * The do-loop tries to sledge-hammer closed the timing hole between
697 * the initial value-read and the polarity-write - if the line value changes
701 * Algorithm comes from Google's msmgpio driver.
712 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
715 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
718 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
722 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
723 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
735 if (d->parent_data) in msm_gpio_irq_mask()
738 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
741 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
743 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
750 * an irq that it's configured for (either edge for edge type or level in msm_gpio_irq_mask()
751 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
753 * status bit is set. There's a bug though, the edge detection logic in msm_gpio_irq_mask()
760 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
764 * while it's masked. in msm_gpio_irq_mask()
767 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
769 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
772 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
774 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
785 if (d->parent_data) in msm_gpio_irq_clear_unmask()
788 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_clear_unmask()
791 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_clear_unmask()
793 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_clear_unmask()
802 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_clear_unmask()
807 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_clear_unmask()
808 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_clear_unmask()
811 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_clear_unmask()
813 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_clear_unmask()
821 if (d->parent_data) in msm_gpio_irq_enable()
824 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
833 if (d->parent_data) in msm_gpio_irq_disable()
836 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
846 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
851 * different due to what's easy to do with our parent, but in principle it's
858 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
864 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
877 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
887 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
888 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
899 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
900 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
905 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
907 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
910 if (g->intr_ack_high) in msm_gpio_irq_ack()
911 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
913 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
916 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
919 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
929 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
930 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
942 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
948 if (d->parent_data) in msm_gpio_irq_set_type()
951 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
952 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
957 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
959 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
964 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
965 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
967 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
973 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
974 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
979 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
980 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
984 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
986 d->hwirq); in msm_gpio_irq_set_type()
989 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
990 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1000 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1001 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1002 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1003 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1006 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1007 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1010 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1011 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1014 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1015 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1020 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1023 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1024 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1025 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1028 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1029 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1032 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1035 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1036 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1041 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1049 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1052 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1073 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1076 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1085 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1086 return -ENODEV; in msm_gpio_irq_reqres()
1088 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1091 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1093 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1094 dev_err(gc->parent, in msm_gpio_irq_reqres()
1096 d->hwirq); in msm_gpio_irq_reqres()
1097 ret = -EINVAL; in msm_gpio_irq_reqres()
1105 * PDC. These GPIOs are direct-connect interrupts to the GIC. in msm_gpio_irq_reqres()
1110 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_reqres()
1115 module_put(gc->owner); in msm_gpio_irq_reqres()
1123 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1124 module_put(gc->owner); in msm_gpio_irq_relres()
1133 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1144 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1164 * Each pin has it's own IRQ status register, so use in msm_gpio_irq_handler()
1167 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1168 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1170 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1171 irq_pin = irq_find_mapping(gc->irq.domain, i); in msm_gpio_irq_handler()
1197 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1198 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1199 if (map->gpio == child) { in msm_gpio_wakeirq()
1200 *parent = map->wakeirq; in msm_gpio_wakeirq()
1210 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1213 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1221 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1226 return -EINVAL; in msm_gpio_init()
1228 chip = &pctrl->chip; in msm_gpio_init()
1229 chip->base = -1; in msm_gpio_init()
1230 chip->ngpio = ngpio; in msm_gpio_init()
1231 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1232 chip->parent = pctrl->dev; in msm_gpio_init()
1233 chip->owner = THIS_MODULE; in msm_gpio_init()
1234 chip->of_node = pctrl->dev->of_node; in msm_gpio_init()
1236 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1238 pctrl->irq_chip.name = "msmgpio"; in msm_gpio_init()
1239 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; in msm_gpio_init()
1240 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; in msm_gpio_init()
1241 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; in msm_gpio_init()
1242 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; in msm_gpio_init()
1243 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; in msm_gpio_init()
1244 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; in msm_gpio_init()
1245 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; in msm_gpio_init()
1246 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; in msm_gpio_init()
1247 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; in msm_gpio_init()
1248 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; in msm_gpio_init()
1249 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; in msm_gpio_init()
1250 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND | in msm_gpio_init()
1254 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1256 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1259 if (!chip->irq.parent_domain) in msm_gpio_init()
1260 return -EPROBE_DEFER; in msm_gpio_init()
1261 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1262 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; in msm_gpio_init()
1264 * Let's skip handling the GPIOs, if the parent irqchip in msm_gpio_init()
1267 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1268 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1269 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1270 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1274 girq = &chip->irq; in msm_gpio_init()
1275 girq->chip = &pctrl->irq_chip; in msm_gpio_init()
1276 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1277 girq->fwnode = pctrl->dev->fwnode; in msm_gpio_init()
1278 girq->num_parents = 1; in msm_gpio_init()
1279 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1281 if (!girq->parents) in msm_gpio_init()
1282 return -ENOMEM; in msm_gpio_init()
1283 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1284 girq->handler = handle_bad_irq; in msm_gpio_init()
1285 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1287 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1289 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1294 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1295 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1300 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1303 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1304 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1305 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1307 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1308 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1321 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1330 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); in msm_ps_hold_poweroff()
1336 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1338 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1340 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1341 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1342 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1343 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1355 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1362 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1378 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1380 return -ENOMEM; in msm_pinctrl_probe()
1382 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1383 pctrl->soc = soc_data; in msm_pinctrl_probe()
1384 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1385 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1386 pctrl->dev->of_node, in msm_pinctrl_probe()
1387 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1389 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1391 if (soc_data->tiles) { in msm_pinctrl_probe()
1392 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1394 soc_data->tiles[i]); in msm_pinctrl_probe()
1395 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1396 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1397 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1401 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1402 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1403 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1405 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1410 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1411 if (pctrl->irq < 0) in msm_pinctrl_probe()
1412 return pctrl->irq; in msm_pinctrl_probe()
1414 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1415 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1416 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1417 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1418 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1419 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1420 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1422 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1423 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1424 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1425 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1434 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1444 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1446 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()