Lines Matching +full:rk3288 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
60 RK3288, enumerator
79 * @offset: if initialized to -1 it will be autocalculated, by specifying
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 { .offset = -1 }, \
182 { .offset = -1 }, \
192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
205 { .offset = -1 }, \
206 { .offset = -1 }, \
207 { .offset = -1 }, \
208 { .offset = -1 }, \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
226 { .offset = -1 }, \
227 { .offset = -1 }, \
228 { .offset = -1 }, \
229 { .offset = -1 }, \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
418 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
419 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
420 return &info->groups[i]; in pinctrl_name_to_group()
433 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
435 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
445 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
448 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
449 if (b->bank_num == num) in bank_num_to_bank()
453 return ERR_PTR(-EINVAL); in bank_num_to_bank()
464 return info->ngroups; in rockchip_get_groups_count()
472 return info->groups[selector].name; in rockchip_get_group_name()
481 if (selector >= info->ngroups) in rockchip_get_group_pins()
482 return -EINVAL; in rockchip_get_group_pins()
484 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
485 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
505 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
507 dev_err(info->dev, "unable to find group for node %pOFn\n", in rockchip_dt_node_to_map()
509 return -EINVAL; in rockchip_dt_node_to_map()
512 map_num += grp->npins; in rockchip_dt_node_to_map()
516 return -ENOMEM; in rockchip_dt_node_to_map()
525 return -EINVAL; in rockchip_dt_node_to_map()
528 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
529 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
534 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
537 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
538 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
539 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
542 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in rockchip_dt_node_to_map()
543 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
783 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
784 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
788 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
789 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
790 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
791 data->pin == pin) in rockchip_get_recalced_mux()
795 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
798 *reg = data->reg; in rockchip_get_recalced_mux()
799 *mask = data->mask; in rockchip_get_recalced_mux()
800 *bit = data->bit; in rockchip_get_recalced_mux()
805 /* cif-d2m0 */
812 /* cif-d2m1 */
819 /* pdm-m0 */
826 /* pdm-m1 */
833 /* uart2-rxm0 */
840 /* uart2-rxm1 */
847 /* uart3-rxm0 */
854 /* uart3-rxm1 */
865 /* spi-0 */
872 /* spi-1 */
879 /* spi-2 */
886 /* i2s-0 */
893 /* i2s-1 */
900 /* emmc-0 */
907 /* emmc-1 */
918 /* non-iomuxed emmc/flash pins on flash-dqs */
926 /* non-iomuxed emmc/flash pins on emmc-clk */
938 /* pwm0-0 */
945 /* pwm0-1 */
952 /* pwm1-0 */
959 /* pwm1-1 */
966 /* pwm2-0 */
973 /* pwm2-1 */
980 /* pwm3-0 */
987 /* pwm3-1 */
994 /* sdio-0_d0 */
1001 /* sdio-1_d0 */
1008 /* spi-0_rx */
1015 /* spi-1_rx */
1022 /* emmc-0_cmd */
1029 /* emmc-1_cmd */
1036 /* uart2-0_rx */
1043 /* uart2-1_rx */
1050 /* uart1-0_rx */
1057 /* uart1-1_rx */
1128 /* i2s-8ch-1-sclktxm0 */
1135 /* i2s-8ch-1-sclkrxm0 */
1142 /* i2s-8ch-1-sclktxm1 */
1149 /* i2s-8ch-1-sclkrxm1 */
1156 /* pdm-clkm0 */
1163 /* pdm-clkm1 */
1170 /* pdm-clkm2 */
1177 /* pdm-clkm-m2 */
1286 /* gmac-m1_rxd0 */
1293 /* gmac-m1-optimized_rxd3 */
1400 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1401 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
1405 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1406 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1407 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1408 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1412 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1415 *loc = data->route_location; in rockchip_get_mux_route()
1416 *reg = data->route_offset; in rockchip_get_mux_route()
1417 *value = data->route_val; in rockchip_get_mux_route()
1424 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1432 return -EINVAL; in rockchip_get_mux()
1434 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1435 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1436 return -EINVAL; in rockchip_get_mux()
1439 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1442 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1443 ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1446 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1447 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1463 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1476 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1480 return -EINVAL; in rockchip_verify_mux()
1482 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1483 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_verify_mux()
1484 return -EINVAL; in rockchip_verify_mux()
1487 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1489 dev_err(info->dev, in rockchip_verify_mux()
1491 return -ENOTSUPP; in rockchip_verify_mux()
1513 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1524 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1527 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", in rockchip_set_mux()
1528 bank->bank_num, pin, mux); in rockchip_set_mux()
1530 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1531 ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1534 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1535 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1551 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1554 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1562 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1565 route_regmap = info->regmap_base; in rockchip_set_mux()
1593 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1596 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1597 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1600 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1604 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1605 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1623 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1626 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1627 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1630 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1634 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1635 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1654 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1657 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1658 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1662 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1665 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1684 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1687 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1688 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1692 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1694 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1695 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1713 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1716 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1717 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1720 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1724 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1725 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1744 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1747 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1748 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1752 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1755 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1771 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1773 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1776 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1791 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1793 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1795 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1807 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1809 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1811 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1827 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1830 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1831 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1832 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1833 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1838 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1839 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1840 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1843 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1844 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1852 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1862 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1865 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1866 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1873 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1877 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1878 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1896 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1899 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1900 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1907 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1911 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1912 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1926 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1928 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1930 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1943 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1945 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1947 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1960 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1962 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1964 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1977 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1979 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1981 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1995 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1998 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1999 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
2006 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
2010 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
2011 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
2026 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
2029 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
2030 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
2037 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
2041 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
2042 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
2058 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
2061 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
2062 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
2065 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2071 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
2075 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
2076 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2088 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
2092 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2093 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
2095 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
2097 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
2098 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
2099 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
2106 { 2, 4, 8, 12, -1, -1, -1, -1 },
2107 { 3, 6, 9, 12, -1, -1, -1, -1 },
2108 { 5, 10, 15, 20, -1, -1, -1, -1 },
2116 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2117 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
2122 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2124 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2136 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
2160 bit -= 16; in rockchip_get_drive_perpin()
2163 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
2165 return -EINVAL; in rockchip_get_drive_perpin()
2175 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
2177 return -EINVAL; in rockchip_get_drive_perpin()
2185 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
2193 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2194 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
2199 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2201 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
2202 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2204 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2206 ret = -EINVAL; in rockchip_set_drive_perpin()
2218 dev_err(info->dev, "unsupported driver strength %d\n", in rockchip_set_drive_perpin()
2233 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
2255 bit -= 16; in rockchip_set_drive_perpin()
2258 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
2260 return -EINVAL; in rockchip_set_drive_perpin()
2269 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
2271 return -EINVAL; in rockchip_set_drive_perpin()
2275 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2301 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2302 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
2309 if (ctrl->type == RK3066B) in rockchip_get_pull()
2312 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2318 switch (ctrl->type) { in rockchip_get_pull()
2327 case RK3288: in rockchip_get_pull()
2331 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2333 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
2337 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_get_pull()
2338 return -EINVAL; in rockchip_get_pull()
2345 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2346 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
2352 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", in rockchip_set_pull()
2353 bank->bank_num, pin_num, pull); in rockchip_set_pull()
2356 if (ctrl->type == RK3066B) in rockchip_set_pull()
2357 return pull ? -EINVAL : 0; in rockchip_set_pull()
2359 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2361 switch (ctrl->type) { in rockchip_set_pull()
2372 case RK3288: in rockchip_set_pull()
2376 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2377 ret = -EINVAL; in rockchip_set_pull()
2387 dev_err(info->dev, "unsupported pull setting %d\n", in rockchip_set_pull()
2393 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2400 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_set_pull()
2401 return -EINVAL; in rockchip_set_pull()
2417 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2419 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2422 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2431 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2432 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
2438 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2453 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2454 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
2460 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
2461 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2463 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2482 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2490 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2499 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2500 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2509 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2510 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2514 dev_dbg(info->dev, "enable function %s group %s\n", in rockchip_pmx_set()
2515 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2521 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2523 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2531 for (cnt--; cnt >= 0; cnt--) in rockchip_pmx_set()
2532 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2546 ret = clk_enable(bank->clk); in rockchip_gpio_get_direction()
2548 dev_err(bank->drvdata->dev, in rockchip_gpio_get_direction()
2549 "failed to enable clock for bank %s\n", bank->name); in rockchip_gpio_get_direction()
2552 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_gpio_get_direction()
2553 clk_disable(bank->clk); in rockchip_gpio_get_direction()
2580 clk_enable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2581 raw_spin_lock_irqsave(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2583 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2589 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2591 raw_spin_unlock_irqrestore(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2592 clk_disable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2605 chip = range->gc; in rockchip_pmx_gpio_set_direction()
2606 pin = offset - chip->base; in rockchip_pmx_gpio_set_direction()
2607 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", in rockchip_pmx_gpio_set_direction()
2608 offset, range->name, pin, input ? "input" : "output"); in rockchip_pmx_gpio_set_direction()
2610 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, in rockchip_pmx_gpio_set_direction()
2629 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2639 case RK3288: in rockchip_pinconf_pull_valid()
2669 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2678 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
2679 return -ENOTSUPP; in rockchip_pinconf_set()
2682 return -EINVAL; in rockchip_pinconf_set()
2684 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2690 rockchip_gpio_set(&bank->gpio_chip, in rockchip_pinconf_set()
2691 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2692 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, in rockchip_pinconf_set()
2693 pin - bank->pin_base, false); in rockchip_pinconf_set()
2698 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
2699 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
2700 return -ENOTSUPP; in rockchip_pinconf_set()
2703 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2708 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2709 return -ENOTSUPP; in rockchip_pinconf_set()
2712 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2717 return -ENOTSUPP; in rockchip_pinconf_set()
2737 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2738 return -EINVAL; in rockchip_pinconf_get()
2746 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
2747 return -ENOTSUPP; in rockchip_pinconf_get()
2749 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2750 return -EINVAL; in rockchip_pinconf_get()
2755 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2757 return -EINVAL; in rockchip_pinconf_get()
2759 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); in rockchip_pinconf_get()
2766 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
2767 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
2768 return -ENOTSUPP; in rockchip_pinconf_get()
2770 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2777 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
2778 return -ENOTSUPP; in rockchip_pinconf_get()
2780 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2787 return -ENOTSUPP; in rockchip_pinconf_get()
2803 { .compatible = "rockchip,gpio-bank" },
2804 { .compatible = "rockchip,rk3188-gpio-bank0" },
2817 info->nfunctions++; in rockchip_pinctrl_child_count()
2818 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
2834 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_groups()
2837 grp->name = np->name; in rockchip_pinctrl_parse_groups()
2847 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
2848 return -EINVAL; in rockchip_pinctrl_parse_groups()
2851 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
2853 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in rockchip_pinctrl_parse_groups()
2855 grp->data = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_groups()
2856 grp->npins, in rockchip_pinctrl_parse_groups()
2859 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
2860 return -ENOMEM; in rockchip_pinctrl_parse_groups()
2871 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2872 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2876 return -EINVAL; in rockchip_pinctrl_parse_groups()
2880 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
2899 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_functions()
2901 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
2904 func->name = np->name; in rockchip_pinctrl_parse_functions()
2905 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
2906 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
2909 func->groups = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_functions()
2910 func->ngroups, sizeof(char *), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
2911 if (!func->groups) in rockchip_pinctrl_parse_functions()
2912 return -ENOMEM; in rockchip_pinctrl_parse_functions()
2915 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
2916 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
2930 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
2931 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
2938 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
2939 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
2941 info->functions = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2942 info->nfunctions, in rockchip_pinctrl_parse_dt()
2945 if (!info->functions) in rockchip_pinctrl_parse_dt()
2946 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2948 info->groups = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2949 info->ngroups, in rockchip_pinctrl_parse_dt()
2952 if (!info->groups) in rockchip_pinctrl_parse_dt()
2953 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2963 dev_err(&pdev->dev, "failed to parse function\n"); in rockchip_pinctrl_parse_dt()
2975 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
2981 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
2982 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
2983 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
2984 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
2985 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
2987 pindesc = devm_kcalloc(&pdev->dev, in rockchip_pinctrl_register()
2988 info->ctrl->nr_pins, sizeof(*pindesc), in rockchip_pinctrl_register()
2991 return -ENOMEM; in rockchip_pinctrl_register()
2993 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
2994 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
2997 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
2998 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
2999 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3000 pdesc->number = k; in rockchip_pinctrl_register()
3001 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", in rockchip_pinctrl_register()
3002 pin_bank->name, pin); in rockchip_pinctrl_register()
3011 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); in rockchip_pinctrl_register()
3012 if (IS_ERR(info->pctl_dev)) { in rockchip_pinctrl_register()
3013 dev_err(&pdev->dev, "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
3014 return PTR_ERR(info->pctl_dev); in rockchip_pinctrl_register()
3017 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { in rockchip_pinctrl_register()
3018 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3019 pin_bank->grange.name = pin_bank->name; in rockchip_pinctrl_register()
3020 pin_bank->grange.id = bank; in rockchip_pinctrl_register()
3021 pin_bank->grange.pin_base = pin_bank->pin_base; in rockchip_pinctrl_register()
3022 pin_bank->grange.base = pin_bank->gpio_chip.base; in rockchip_pinctrl_register()
3023 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; in rockchip_pinctrl_register()
3024 pin_bank->grange.gc = &pin_bank->gpio_chip; in rockchip_pinctrl_register()
3025 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); in rockchip_pinctrl_register()
3038 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; in rockchip_gpio_set()
3042 clk_enable(bank->clk); in rockchip_gpio_set()
3043 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
3051 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
3052 clk_disable(bank->clk); in rockchip_gpio_set()
3064 clk_enable(bank->clk); in rockchip_gpio_get()
3065 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_gpio_get()
3066 clk_disable(bank->clk); in rockchip_gpio_get()
3079 return pinctrl_gpio_direction_input(gc->base + offset); in rockchip_gpio_direction_input()
3091 return pinctrl_gpio_direction_output(gc->base + offset); in rockchip_gpio_direction_output()
3098 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; in rockchip_gpio_set_debounce()
3102 clk_enable(bank->clk); in rockchip_gpio_set_debounce()
3103 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
3112 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
3113 clk_disable(bank->clk); in rockchip_gpio_set_debounce()
3137 * still return -ENOTSUPP as before, to make sure the caller in rockchip_gpio_set_config()
3140 return -ENOTSUPP; in rockchip_gpio_set_config()
3142 return -ENOTSUPP; in rockchip_gpio_set_config()
3155 if (!bank->domain) in rockchip_gpio_to_irq()
3156 return -ENXIO; in rockchip_gpio_to_irq()
3158 clk_enable(bank->clk); in rockchip_gpio_to_irq()
3159 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
3160 clk_disable(bank->clk); in rockchip_gpio_to_irq()
3162 return (virq) ? : -ENXIO; in rockchip_gpio_to_irq()
3188 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
3192 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
3199 virq = irq_find_mapping(bank->domain, irq); in rockchip_irq_demux()
3202 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); in rockchip_irq_demux()
3206 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
3212 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
3216 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
3218 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
3220 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3227 bank->reg_base + GPIO_INT_POLARITY); in rockchip_irq_demux()
3229 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
3232 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3246 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type()
3247 u32 mask = BIT(d->hwirq); in rockchip_irq_set_type()
3255 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); in rockchip_irq_set_type()
3259 clk_enable(bank->clk); in rockchip_irq_set_type()
3260 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3262 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3264 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3266 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3273 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3276 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
3277 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
3281 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
3288 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_set_type()
3295 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3300 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3305 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3310 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3316 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3317 clk_disable(bank->clk); in rockchip_irq_set_type()
3318 return -EINVAL; in rockchip_irq_set_type()
3321 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
3322 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
3325 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3326 clk_disable(bank->clk); in rockchip_irq_set_type()
3334 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend()
3336 clk_enable(bank->clk); in rockchip_irq_suspend()
3337 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); in rockchip_irq_suspend()
3338 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); in rockchip_irq_suspend()
3339 clk_disable(bank->clk); in rockchip_irq_suspend()
3345 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume()
3347 clk_enable(bank->clk); in rockchip_irq_resume()
3348 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); in rockchip_irq_resume()
3349 clk_disable(bank->clk); in rockchip_irq_resume()
3355 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_enable()
3357 clk_enable(bank->clk); in rockchip_irq_enable()
3364 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_disable()
3367 clk_disable(bank->clk); in rockchip_irq_disable()
3373 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_interrupts_register()
3374 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_interrupts_register()
3380 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_interrupts_register()
3381 if (!bank->valid) { in rockchip_interrupts_register()
3382 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_interrupts_register()
3383 bank->name); in rockchip_interrupts_register()
3387 ret = clk_enable(bank->clk); in rockchip_interrupts_register()
3389 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", in rockchip_interrupts_register()
3390 bank->name); in rockchip_interrupts_register()
3394 bank->domain = irq_domain_add_linear(bank->of_node, 32, in rockchip_interrupts_register()
3396 if (!bank->domain) { in rockchip_interrupts_register()
3397 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", in rockchip_interrupts_register()
3398 bank->name); in rockchip_interrupts_register()
3399 clk_disable(bank->clk); in rockchip_interrupts_register()
3403 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
3407 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
3408 bank->name); in rockchip_interrupts_register()
3409 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
3410 clk_disable(bank->clk); in rockchip_interrupts_register()
3414 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
3415 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
3416 gc->private = bank; in rockchip_interrupts_register()
3417 gc->chip_types[0].regs.mask = GPIO_INTMASK; in rockchip_interrupts_register()
3418 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; in rockchip_interrupts_register()
3419 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in rockchip_interrupts_register()
3420 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in rockchip_interrupts_register()
3421 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in rockchip_interrupts_register()
3422 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; in rockchip_interrupts_register()
3423 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; in rockchip_interrupts_register()
3424 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; in rockchip_interrupts_register()
3425 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; in rockchip_interrupts_register()
3426 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; in rockchip_interrupts_register()
3427 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; in rockchip_interrupts_register()
3428 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
3435 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); in rockchip_interrupts_register()
3436 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); in rockchip_interrupts_register()
3437 gc->mask_cache = 0xffffffff; in rockchip_interrupts_register()
3439 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
3441 clk_disable(bank->clk); in rockchip_interrupts_register()
3450 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_gpiolib_register()
3451 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_register()
3456 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_register()
3457 if (!bank->valid) { in rockchip_gpiolib_register()
3458 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_gpiolib_register()
3459 bank->name); in rockchip_gpiolib_register()
3463 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
3465 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
3466 gc->base = bank->pin_base; in rockchip_gpiolib_register()
3467 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
3468 gc->parent = &pdev->dev; in rockchip_gpiolib_register()
3469 gc->of_node = bank->of_node; in rockchip_gpiolib_register()
3470 gc->label = bank->name; in rockchip_gpiolib_register()
3474 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", in rockchip_gpiolib_register()
3475 gc->label, ret); in rockchip_gpiolib_register()
3485 for (--i, --bank; i >= 0; --i, --bank) { in rockchip_gpiolib_register()
3486 if (!bank->valid) in rockchip_gpiolib_register()
3488 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
3496 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_gpiolib_unregister()
3497 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_unregister()
3500 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_unregister()
3501 if (!bank->valid) in rockchip_gpiolib_unregister()
3503 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_unregister()
3515 if (of_address_to_resource(bank->of_node, 0, &res)) { in rockchip_get_bank_data()
3516 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3517 return -ENOENT; in rockchip_get_bank_data()
3520 bank->reg_base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3521 if (IS_ERR(bank->reg_base)) in rockchip_get_bank_data()
3522 return PTR_ERR(bank->reg_base); in rockchip_get_bank_data()
3525 * special case, where parts of the pull setting-registers are in rockchip_get_bank_data()
3528 if (of_device_is_compatible(bank->of_node, in rockchip_get_bank_data()
3529 "rockchip,rk3188-gpio-bank0")) { in rockchip_get_bank_data()
3532 node = of_parse_phandle(bank->of_node->parent, in rockchip_get_bank_data()
3535 if (of_address_to_resource(bank->of_node, 1, &res)) { in rockchip_get_bank_data()
3536 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3537 return -ENOENT; in rockchip_get_bank_data()
3540 base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3544 resource_size(&res) - 4; in rockchip_get_bank_data()
3546 "rockchip,rk3188-gpio-bank0-pull"; in rockchip_get_bank_data()
3547 bank->regmap_pull = devm_regmap_init_mmio(info->dev, in rockchip_get_bank_data()
3554 bank->irq = irq_of_parse_and_map(bank->of_node, 0); in rockchip_get_bank_data()
3556 bank->clk = of_clk_get(bank->of_node, 0); in rockchip_get_bank_data()
3557 if (IS_ERR(bank->clk)) in rockchip_get_bank_data()
3558 return PTR_ERR(bank->clk); in rockchip_get_bank_data()
3560 return clk_prepare(bank->clk); in rockchip_get_bank_data()
3571 struct device_node *node = pdev->dev.of_node; in rockchip_pinctrl_get_soc_data()
3578 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
3581 if (!of_find_property(np, "gpio-controller", NULL)) in rockchip_pinctrl_get_soc_data()
3584 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3585 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3586 if (!strcmp(bank->name, np->name)) { in rockchip_pinctrl_get_soc_data()
3587 bank->of_node = np; in rockchip_pinctrl_get_soc_data()
3590 bank->valid = true; in rockchip_pinctrl_get_soc_data()
3597 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
3598 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
3599 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
3600 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
3601 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3602 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3605 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3606 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3607 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3608 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3612 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3613 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3616 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3620 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3621 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3622 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3624 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3626 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3631 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3632 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3633 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3635 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3637 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3641 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3642 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
3648 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
3651 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3658 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3660 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
3661 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
3666 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3674 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3675 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3678 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3679 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
3680 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3684 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3685 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3688 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3689 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
3690 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3706 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
3712 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save in rockchip_pinctrl_suspend()
3715 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
3716 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
3719 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
3730 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
3737 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
3746 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
3748 struct device_node *np = pdev->dev.of_node, *node; in rockchip_pinctrl_probe()
3753 if (!dev->of_node) { in rockchip_pinctrl_probe()
3755 return -ENODEV; in rockchip_pinctrl_probe()
3760 return -ENOMEM; in rockchip_pinctrl_probe()
3762 info->dev = dev; in rockchip_pinctrl_probe()
3767 return -EINVAL; in rockchip_pinctrl_probe()
3769 info->ctrl = ctrl; in rockchip_pinctrl_probe()
3773 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3774 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
3775 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
3778 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
3782 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3784 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, in rockchip_pinctrl_probe()
3787 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
3788 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
3791 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3793 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
3798 resource_size(res) - 4; in rockchip_pinctrl_probe()
3799 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
3800 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, in rockchip_pinctrl_probe()
3809 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3810 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
3811 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
3855 .label = "PX30-GPIO",
3879 .label = "RV1108-GPIO",
3900 .label = "RK2928-GPIO",
3915 .label = "RK3036-GPIO",
3933 .label = "RK3066a-GPIO",
3949 .label = "RK3066b-GPIO",
3964 .label = "RK3128-GPIO",
3984 .label = "RK3188-GPIO",
4002 .label = "RK3228-GPIO",
4003 .type = RK3288,
4046 .label = "RK3288-GPIO",
4047 .type = RK3288,
4082 .label = "RK3308-GPIO",
4111 .label = "RK3328-GPIO",
4112 .type = RK3288,
4137 .label = "RK3368-GPIO",
4157 -1,
4158 -1,
4201 .label = "RK3399-GPIO",
4214 { .compatible = "rockchip,px30-pinctrl",
4216 { .compatible = "rockchip,rv1108-pinctrl",
4218 { .compatible = "rockchip,rk2928-pinctrl",
4220 { .compatible = "rockchip,rk3036-pinctrl",
4222 { .compatible = "rockchip,rk3066a-pinctrl",
4224 { .compatible = "rockchip,rk3066b-pinctrl",
4226 { .compatible = "rockchip,rk3128-pinctrl",
4228 { .compatible = "rockchip,rk3188-pinctrl",
4230 { .compatible = "rockchip,rk3228-pinctrl",
4232 { .compatible = "rockchip,rk3288-pinctrl",
4234 { .compatible = "rockchip,rk3308-pinctrl",
4236 { .compatible = "rockchip,rk3328-pinctrl",
4238 { .compatible = "rockchip,rk3368-pinctrl",
4240 { .compatible = "rockchip,rk3399-pinctrl",
4248 .name = "rockchip-pinctrl",