Lines Matching full:bank
125 * @reg_base: register base of the gpio bank
127 * @clk: clock of the gpio bank
128 * @irq: interrupt of the gpio bank
131 * @nr_pins: number of pins in this bank
132 * @name: name of the bank
133 * @bank_num: number of the bank, to account for holes
134 * @iomux: array describing the 4 iomux sources of the bank
135 * @drv: array describing the 4 drive strength sources of the bank
136 * @pull_type: array describing the 4 pull type sources of the bank
138 * @of_node: dt node of this bank
140 * @domain: irqdomain of the gpio bank
143 * @slock: spinlock for the gpio bank
146 * @route_mask: bits describing the routing pins of per bank
295 * @num: bank number.
317 * @bank_num: bank number.
348 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
351 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
354 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
427 * given a pin number that is local to a pin controller, find out the pin bank
428 * and the register base of the pin bank.
780 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
783 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
790 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1397 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1400 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1407 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1422 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1424 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1434 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1439 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1442 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1446 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1447 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1463 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1464 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_get_mux()
1473 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, in rockchip_verify_mux() argument
1476 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1482 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1487 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1507 * @bank: pin bank to change
1511 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rockchip_set_mux() argument
1513 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1520 ret = rockchip_verify_mux(bank, pin, mux); in rockchip_set_mux()
1524 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1528 bank->bank_num, pin, mux); in rockchip_set_mux()
1530 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1534 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1535 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1551 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1552 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_set_mux()
1554 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1555 if (rockchip_get_mux_route(bank, pin, mux, &route_location, in rockchip_set_mux()
1589 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_pull_reg_and_bit() argument
1593 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1595 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_pull_reg_and_bit()
1596 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1603 /* correct the offset, as we're starting with the 2nd bank */ in px30_calc_pull_reg_and_bit()
1605 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1619 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_drv_reg_and_bit() argument
1623 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1625 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_drv_reg_and_bit()
1626 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1633 /* correct the offset, as we're starting with the 2nd bank */ in px30_calc_drv_reg_and_bit()
1635 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1649 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_schmitt_reg_and_bit() argument
1654 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1657 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1665 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1680 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_pull_reg_and_bit() argument
1684 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1686 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_pull_reg_and_bit()
1687 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1693 /* correct the offset, as we're starting with the 2nd bank */ in rv1108_calc_pull_reg_and_bit()
1695 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1709 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_drv_reg_and_bit() argument
1713 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1715 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_drv_reg_and_bit()
1716 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1723 /* correct the offset, as we're starting with the 2nd bank */ in rv1108_calc_drv_reg_and_bit()
1725 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1739 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_schmitt_reg_and_bit() argument
1744 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1747 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1755 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1767 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_schmitt_reg_and_bit() argument
1771 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1776 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1787 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk2928_calc_pull_reg_and_bit() argument
1791 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1795 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1803 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3128_calc_pull_reg_and_bit() argument
1807 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1811 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1823 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3188_calc_pull_reg_and_bit() argument
1827 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1829 /* The first 12 pins of the first bank are located elsewhere */ in rk3188_calc_pull_reg_and_bit()
1830 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1832 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1844 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1858 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_pull_reg_and_bit() argument
1862 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1864 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_pull_reg_and_bit()
1865 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1876 /* correct the offset, as we're starting with the 2nd bank */ in rk3288_calc_pull_reg_and_bit()
1878 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1892 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_drv_reg_and_bit() argument
1896 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1898 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_drv_reg_and_bit()
1899 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1910 /* correct the offset, as we're starting with the 2nd bank */ in rk3288_calc_drv_reg_and_bit()
1912 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1922 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3228_calc_pull_reg_and_bit() argument
1926 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1930 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1939 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3228_calc_drv_reg_and_bit() argument
1943 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1947 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1956 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_pull_reg_and_bit() argument
1960 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1964 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1973 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_drv_reg_and_bit() argument
1977 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1981 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1991 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_pull_reg_and_bit() argument
1995 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1997 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_pull_reg_and_bit()
1998 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
2009 /* correct the offset, as we're starting with the 2nd bank */ in rk3368_calc_pull_reg_and_bit()
2011 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
2022 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_drv_reg_and_bit() argument
2026 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
2028 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_drv_reg_and_bit()
2029 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
2040 /* correct the offset, as we're starting with the 2nd bank */ in rk3368_calc_drv_reg_and_bit()
2042 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
2054 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_pull_reg_and_bit() argument
2058 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
2061 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
2065 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2074 /* correct the offset, as we're starting with the 3rd bank */ in rk3399_calc_pull_reg_and_bit()
2076 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2084 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_drv_reg_and_bit() argument
2088 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
2092 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2097 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
2098 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
2099 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
2113 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, in rockchip_get_drive_perpin() argument
2116 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2122 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2124 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2190 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, in rockchip_set_drive_perpin() argument
2193 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2199 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2202 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2204 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2299 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) in rockchip_get_pull() argument
2301 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2312 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2331 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2342 static int rockchip_set_pull(struct rockchip_pin_bank *bank, in rockchip_set_pull() argument
2345 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2353 bank->bank_num, pin_num, pull); in rockchip_set_pull()
2359 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2376 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2412 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3328_calc_schmitt_reg_and_bit() argument
2417 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2422 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2429 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) in rockchip_get_schmitt() argument
2431 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2438 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2450 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, in rockchip_set_schmitt() argument
2453 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2461 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2463 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2511 struct rockchip_pin_bank *bank; in rockchip_pmx_set() local
2522 bank = pin_to_bank(info, pins[cnt]); in rockchip_pmx_set()
2523 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2532 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2542 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); in rockchip_gpio_get_direction() local
2546 ret = clk_enable(bank->clk); in rockchip_gpio_get_direction()
2548 dev_err(bank->drvdata->dev, in rockchip_gpio_get_direction()
2549 "failed to enable clock for bank %s\n", bank->name); in rockchip_gpio_get_direction()
2552 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_gpio_get_direction()
2553 clk_disable(bank->clk); in rockchip_gpio_get_direction()
2569 struct rockchip_pin_bank *bank; in _rockchip_pmx_gpio_set_direction() local
2574 bank = gpiochip_get_data(chip); in _rockchip_pmx_gpio_set_direction()
2576 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); in _rockchip_pmx_gpio_set_direction()
2580 clk_enable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2581 raw_spin_lock_irqsave(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2583 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2589 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2591 raw_spin_unlock_irqrestore(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2592 clk_disable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2657 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); in rockchip_pinconf_set() local
2669 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2684 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2690 rockchip_gpio_set(&bank->gpio_chip, in rockchip_pinconf_set()
2691 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2692 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, in rockchip_pinconf_set()
2693 pin - bank->pin_base, false); in rockchip_pinconf_set()
2702 rc = rockchip_set_drive_perpin(bank, in rockchip_pinconf_set()
2703 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2711 rc = rockchip_set_schmitt(bank, in rockchip_pinconf_set()
2712 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2730 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); in rockchip_pinconf_get() local
2737 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2749 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2755 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2759 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); in rockchip_pinconf_get()
2770 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2780 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2803 { .compatible = "rockchip,gpio-bank" },
2827 struct rockchip_pin_bank *bank; in rockchip_pinctrl_parse_groups() local
2840 * the binding format is rockchip,pins = <bank pin mux CONFIG>, in rockchip_pinctrl_parse_groups()
2867 bank = bank_num_to_bank(info, num); in rockchip_pinctrl_parse_groups()
2868 if (IS_ERR(bank)) in rockchip_pinctrl_parse_groups()
2869 return PTR_ERR(bank); in rockchip_pinctrl_parse_groups()
2871 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2978 int pin, bank, ret; in rockchip_pinctrl_register() local
2997 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
2998 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3017 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { in rockchip_pinctrl_register()
3018 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3020 pin_bank->grange.id = bank; in rockchip_pinctrl_register()
3037 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set() local
3038 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; in rockchip_gpio_set()
3042 clk_enable(bank->clk); in rockchip_gpio_set()
3043 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
3051 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
3052 clk_disable(bank->clk); in rockchip_gpio_set()
3061 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_get() local
3064 clk_enable(bank->clk); in rockchip_gpio_get()
3065 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_gpio_get()
3066 clk_disable(bank->clk); in rockchip_gpio_get()
3097 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set_debounce() local
3098 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; in rockchip_gpio_set_debounce()
3102 clk_enable(bank->clk); in rockchip_gpio_set_debounce()
3103 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
3112 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
3113 clk_disable(bank->clk); in rockchip_gpio_set_debounce()
3152 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_to_irq() local
3155 if (!bank->domain) in rockchip_gpio_to_irq()
3158 clk_enable(bank->clk); in rockchip_gpio_to_irq()
3159 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
3160 clk_disable(bank->clk); in rockchip_gpio_to_irq()
3185 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); in rockchip_irq_demux() local
3188 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
3192 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
3199 virq = irq_find_mapping(bank->domain, irq); in rockchip_irq_demux()
3202 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); in rockchip_irq_demux()
3206 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
3212 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
3216 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
3218 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
3220 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3227 bank->reg_base + GPIO_INT_POLARITY); in rockchip_irq_demux()
3229 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
3232 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3246 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type() local
3255 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); in rockchip_irq_set_type()
3259 clk_enable(bank->clk); in rockchip_irq_set_type()
3260 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3262 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3264 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3266 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3273 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3281 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
3288 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_set_type()
3295 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3300 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3305 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3310 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3316 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3317 clk_disable(bank->clk); in rockchip_irq_set_type()
3325 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3326 clk_disable(bank->clk); in rockchip_irq_set_type()
3334 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend() local
3336 clk_enable(bank->clk); in rockchip_irq_suspend()
3337 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); in rockchip_irq_suspend()
3339 clk_disable(bank->clk); in rockchip_irq_suspend()
3345 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume() local
3347 clk_enable(bank->clk); in rockchip_irq_resume()
3348 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); in rockchip_irq_resume()
3349 clk_disable(bank->clk); in rockchip_irq_resume()
3355 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_enable() local
3357 clk_enable(bank->clk); in rockchip_irq_enable()
3364 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_disable() local
3367 clk_disable(bank->clk); in rockchip_irq_disable()
3374 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_interrupts_register() local
3380 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_interrupts_register()
3381 if (!bank->valid) { in rockchip_interrupts_register()
3382 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_interrupts_register()
3383 bank->name); in rockchip_interrupts_register()
3387 ret = clk_enable(bank->clk); in rockchip_interrupts_register()
3389 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", in rockchip_interrupts_register()
3390 bank->name); in rockchip_interrupts_register()
3394 bank->domain = irq_domain_add_linear(bank->of_node, 32, in rockchip_interrupts_register()
3396 if (!bank->domain) { in rockchip_interrupts_register()
3397 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", in rockchip_interrupts_register()
3398 bank->name); in rockchip_interrupts_register()
3399 clk_disable(bank->clk); in rockchip_interrupts_register()
3403 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
3407 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
3408 bank->name); in rockchip_interrupts_register()
3409 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
3410 clk_disable(bank->clk); in rockchip_interrupts_register()
3414 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
3415 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
3416 gc->private = bank; in rockchip_interrupts_register()
3428 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
3435 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); in rockchip_interrupts_register()
3436 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); in rockchip_interrupts_register()
3439 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
3440 rockchip_irq_demux, bank); in rockchip_interrupts_register()
3441 clk_disable(bank->clk); in rockchip_interrupts_register()
3451 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_register() local
3456 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_register()
3457 if (!bank->valid) { in rockchip_gpiolib_register()
3458 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_gpiolib_register()
3459 bank->name); in rockchip_gpiolib_register()
3463 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
3465 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
3466 gc->base = bank->pin_base; in rockchip_gpiolib_register()
3467 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
3469 gc->of_node = bank->of_node; in rockchip_gpiolib_register()
3470 gc->label = bank->name; in rockchip_gpiolib_register()
3472 ret = gpiochip_add_data(gc, bank); in rockchip_gpiolib_register()
3485 for (--i, --bank; i >= 0; --i, --bank) { in rockchip_gpiolib_register()
3486 if (!bank->valid) in rockchip_gpiolib_register()
3488 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
3497 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_unregister() local
3500 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_unregister()
3501 if (!bank->valid) in rockchip_gpiolib_unregister()
3503 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_unregister()
3509 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, in rockchip_get_bank_data() argument
3515 if (of_address_to_resource(bank->of_node, 0, &res)) { in rockchip_get_bank_data()
3516 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3520 bank->reg_base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3521 if (IS_ERR(bank->reg_base)) in rockchip_get_bank_data()
3522 return PTR_ERR(bank->reg_base); in rockchip_get_bank_data()
3528 if (of_device_is_compatible(bank->of_node, in rockchip_get_bank_data()
3532 node = of_parse_phandle(bank->of_node->parent, in rockchip_get_bank_data()
3535 if (of_address_to_resource(bank->of_node, 1, &res)) { in rockchip_get_bank_data()
3536 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3547 bank->regmap_pull = devm_regmap_init_mmio(info->dev, in rockchip_get_bank_data()
3554 bank->irq = irq_of_parse_and_map(bank->of_node, 0); in rockchip_get_bank_data()
3556 bank->clk = of_clk_get(bank->of_node, 0); in rockchip_get_bank_data()
3557 if (IS_ERR(bank->clk)) in rockchip_get_bank_data()
3558 return PTR_ERR(bank->clk); in rockchip_get_bank_data()
3560 return clk_prepare(bank->clk); in rockchip_get_bank_data()
3574 struct rockchip_pin_bank *bank; in rockchip_pinctrl_get_soc_data() local
3584 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3585 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3586 if (!strcmp(bank->name, np->name)) { in rockchip_pinctrl_get_soc_data()
3587 bank->of_node = np; in rockchip_pinctrl_get_soc_data()
3589 if (!rockchip_get_bank_data(bank, d)) in rockchip_pinctrl_get_soc_data()
3590 bank->valid = true; in rockchip_pinctrl_get_soc_data()
3601 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3602 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3605 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3606 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3607 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3608 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3612 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3613 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3616 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3641 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3674 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3678 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3680 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3684 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3688 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3690 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()