Lines Matching +full:pctrl +full:- +full:syscon
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
9 #include <linux/mfd/syscon.h>
16 #include <linux/pinctrl/pinconf-generic.h>
47 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
48 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
108 spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
113 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
122 spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
127 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
134 seq_printf(s, "-- module %d [gpio%d - %d]\n", in npcmgpio_dbg_show()
135 bank->gc.base / bank->gc.ngpio, in npcmgpio_dbg_show()
136 bank->gc.base, in npcmgpio_dbg_show()
137 bank->gc.base + bank->gc.ngpio); in npcmgpio_dbg_show()
139 ioread32(bank->base + NPCM7XX_GP_N_DIN), in npcmgpio_dbg_show()
140 ioread32(bank->base + NPCM7XX_GP_N_DOUT), in npcmgpio_dbg_show()
141 ioread32(bank->base + NPCM7XX_GP_N_IEM), in npcmgpio_dbg_show()
142 ioread32(bank->base + NPCM7XX_GP_N_OE)); in npcmgpio_dbg_show()
144 ioread32(bank->base + NPCM7XX_GP_N_PU), in npcmgpio_dbg_show()
145 ioread32(bank->base + NPCM7XX_GP_N_PD), in npcmgpio_dbg_show()
146 ioread32(bank->base + NPCM7XX_GP_N_DBNC), in npcmgpio_dbg_show()
147 ioread32(bank->base + NPCM7XX_GP_N_POL)); in npcmgpio_dbg_show()
149 ioread32(bank->base + NPCM7XX_GP_N_EVTYP), in npcmgpio_dbg_show()
150 ioread32(bank->base + NPCM7XX_GP_N_EVBE), in npcmgpio_dbg_show()
151 ioread32(bank->base + NPCM7XX_GP_N_EVEN), in npcmgpio_dbg_show()
152 ioread32(bank->base + NPCM7XX_GP_N_EVST)); in npcmgpio_dbg_show()
154 ioread32(bank->base + NPCM7XX_GP_N_OTYP), in npcmgpio_dbg_show()
155 ioread32(bank->base + NPCM7XX_GP_N_OSRC), in npcmgpio_dbg_show()
156 ioread32(bank->base + NPCM7XX_GP_N_ODSC)); in npcmgpio_dbg_show()
158 ioread32(bank->base + NPCM7XX_GP_N_OBL0), in npcmgpio_dbg_show()
159 ioread32(bank->base + NPCM7XX_GP_N_OBL1), in npcmgpio_dbg_show()
160 ioread32(bank->base + NPCM7XX_GP_N_OBL2), in npcmgpio_dbg_show()
161 ioread32(bank->base + NPCM7XX_GP_N_OBL3)); in npcmgpio_dbg_show()
163 ioread32(bank->base + NPCM7XX_GP_N_SPLCK), in npcmgpio_dbg_show()
164 ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); in npcmgpio_dbg_show()
172 ret = pinctrl_gpio_direction_input(offset + chip->base); in npcmgpio_direction_input()
176 return bank->direction_input(chip, offset); in npcmgpio_direction_input()
186 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset, in npcmgpio_direction_output()
189 ret = pinctrl_gpio_direction_output(offset + chip->base); in npcmgpio_direction_output()
193 return bank->direction_output(chip, offset, value); in npcmgpio_direction_output()
201 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset); in npcmgpio_gpio_request()
202 ret = pinctrl_gpio_request(offset + chip->base); in npcmgpio_gpio_request()
206 return bank->request(chip, offset); in npcmgpio_gpio_request()
211 dev_dbg(chip->parent, "gpio_free: offset%d\n", offset); in npcmgpio_gpio_free()
212 pinctrl_gpio_free(offset + chip->base); in npcmgpio_gpio_free()
227 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); in npcmgpio_irq_handler()
228 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); in npcmgpio_irq_handler()
229 dev_dbg(chip->parent_device, "==> got irq sts %.8x %.8x\n", sts, in npcmgpio_irq_handler()
234 generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit)); in npcmgpio_irq_handler()
242 unsigned int gpio = BIT(d->hwirq); in npcmgpio_set_irq_type()
244 dev_dbg(d->chip->parent_device, "setirqtype: %u.%u = %u\n", gpio, in npcmgpio_set_irq_type()
245 d->irq, type); in npcmgpio_set_irq_type()
248 dev_dbg(d->chip->parent_device, "edge.rising\n"); in npcmgpio_set_irq_type()
249 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
250 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
253 dev_dbg(d->chip->parent_device, "edge.falling\n"); in npcmgpio_set_irq_type()
254 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
255 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
258 dev_dbg(d->chip->parent_device, "edge.both\n"); in npcmgpio_set_irq_type()
259 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
262 dev_dbg(d->chip->parent_device, "level.low\n"); in npcmgpio_set_irq_type()
263 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
266 dev_dbg(d->chip->parent_device, "level.high\n"); in npcmgpio_set_irq_type()
267 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
270 dev_dbg(d->chip->parent_device, "invalid irq type\n"); in npcmgpio_set_irq_type()
271 return -EINVAL; in npcmgpio_set_irq_type()
275 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
279 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
290 unsigned int gpio = d->hwirq; in npcmgpio_irq_ack()
292 dev_dbg(d->chip->parent_device, "irq_ack: %u.%u\n", gpio, d->irq); in npcmgpio_irq_ack()
293 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); in npcmgpio_irq_ack()
301 unsigned int gpio = d->hwirq; in npcmgpio_irq_mask()
304 dev_dbg(d->chip->parent_device, "irq_mask: %u.%u\n", gpio, d->irq); in npcmgpio_irq_mask()
305 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); in npcmgpio_irq_mask()
313 unsigned int gpio = d->hwirq; in npcmgpio_irq_unmask()
316 dev_dbg(d->chip->parent_device, "irq_unmask: %u.%u\n", gpio, d->irq); in npcmgpio_irq_unmask()
317 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); in npcmgpio_irq_unmask()
323 unsigned int gpio = d->hwirq; in npcmgpio_irq_startup()
325 /* active-high, input, clear interrupt, enable interrupt */ in npcmgpio_irq_startup()
326 dev_dbg(d->chip->parent_device, "startup: %u.%u\n", gpio, d->irq); in npcmgpio_irq_startup()
335 .name = "NPCM7XX-GPIO-IRQ",
1420 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) { in npcm7xx_setfunc()
1421 if (cfg->reg0) in npcm7xx_setfunc()
1422 regmap_update_bits(gcr_regmap, cfg->reg0, in npcm7xx_setfunc()
1423 BIT(cfg->bit0), in npcm7xx_setfunc()
1424 !!(cfg->fn0 == mode) ? in npcm7xx_setfunc()
1425 BIT(cfg->bit0) : 0); in npcm7xx_setfunc()
1426 if (cfg->reg1) in npcm7xx_setfunc()
1427 regmap_update_bits(gcr_regmap, cfg->reg1, in npcm7xx_setfunc()
1428 BIT(cfg->bit1), in npcm7xx_setfunc()
1429 !!(cfg->fn1 == mode) ? in npcm7xx_setfunc()
1430 BIT(cfg->bit1) : 0); in npcm7xx_setfunc()
1431 if (cfg->reg2) in npcm7xx_setfunc()
1432 regmap_update_bits(gcr_regmap, cfg->reg2, in npcm7xx_setfunc()
1433 BIT(cfg->bit2), in npcm7xx_setfunc()
1434 !!(cfg->fn2 == mode) ? in npcm7xx_setfunc()
1435 BIT(cfg->bit2) : 0); in npcm7xx_setfunc()
1445 int gpio = (pin % bank->gc.ngpio); in npcm7xx_get_slew_rate()
1449 return ioread32(bank->base + NPCM7XX_GP_N_OSRC) in npcm7xx_get_slew_rate()
1457 return -EINVAL; in npcm7xx_get_slew_rate()
1465 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_set_slew_rate()
1470 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, in npcm7xx_set_slew_rate()
1474 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, in npcm7xx_set_slew_rate()
1478 return -EINVAL; in npcm7xx_set_slew_rate()
1493 return -EINVAL; in npcm7xx_set_slew_rate()
1497 return -EINVAL; in npcm7xx_set_slew_rate()
1506 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_get_drive_strength()
1507 int gpio = (pin % bank->gc.ngpio); in npcm7xx_get_drive_strength()
1515 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) in npcm7xx_get_drive_strength()
1518 dev_dbg(bank->gc.parent, in npcm7xx_get_drive_strength()
1523 return -EINVAL; in npcm7xx_get_drive_strength()
1532 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_set_drive_strength()
1533 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_set_drive_strength()
1537 return -ENOTSUPP; in npcm7xx_set_drive_strength()
1539 dev_dbg(bank->gc.parent, in npcm7xx_set_drive_strength()
1541 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); in npcm7xx_set_drive_strength()
1544 dev_dbg(bank->gc.parent, in npcm7xx_set_drive_strength()
1546 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); in npcm7xx_set_drive_strength()
1550 return -ENOTSUPP; in npcm7xx_set_drive_strength()
1564 dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups)); in npcm7xx_get_groups_count()
1592 dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name); in npcm7xx_dt_node_to_map()
1642 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group, in npcm7xx_pinmux_set_mux()
1645 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins, in npcm7xx_pinmux_set_mux()
1658 dev_err(npcm->dev, "invalid range\n"); in npcm7xx_gpio_request_enable()
1659 return -EINVAL; in npcm7xx_gpio_request_enable()
1661 if (!range->gc) { in npcm7xx_gpio_request_enable()
1662 dev_err(npcm->dev, "invalid gpiochip\n"); in npcm7xx_gpio_request_enable()
1663 return -EINVAL; in npcm7xx_gpio_request_enable()
1666 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio); in npcm7xx_gpio_request_enable()
1679 virq = irq_find_mapping(npcm->domain, offset); in npcm7xx_gpio_request_free()
1691 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; in npcm_gpio_set_direction()
1692 int gpio = BIT(offset % bank->gc.ngpio); in npcm_gpio_set_direction()
1694 dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, in npcm_gpio_set_direction()
1697 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); in npcm_gpio_set_direction()
1699 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); in npcm_gpio_set_direction()
1721 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_config_get()
1722 int gpio = (pin % bank->gc.ngpio); in npcm7xx_config_get()
1731 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; in npcm7xx_config_get()
1732 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; in npcm7xx_config_get()
1742 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; in npcm7xx_config_get()
1743 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; in npcm7xx_config_get()
1750 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); in npcm7xx_config_get()
1753 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; in npcm7xx_config_get()
1756 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; in npcm7xx_config_get()
1764 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin); in npcm7xx_config_get()
1769 return -ENOTSUPP; in npcm7xx_config_get()
1773 return -EINVAL; in npcm7xx_config_get()
1784 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_config_set_one()
1785 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_config_set_one()
1787 dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); in npcm7xx_config_set_one()
1790 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1791 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1794 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1795 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1798 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1799 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1802 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); in npcm7xx_config_set_one()
1803 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); in npcm7xx_config_set_one()
1806 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); in npcm7xx_config_set_one()
1807 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); in npcm7xx_config_set_one()
1810 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); in npcm7xx_config_set_one()
1813 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); in npcm7xx_config_set_one()
1816 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); in npcm7xx_config_set_one()
1819 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); in npcm7xx_config_set_one()
1823 return -ENOTSUPP; in npcm7xx_config_set_one()
1836 while (num_configs--) { in npcm7xx_config_set()
1853 .name = "npcm7xx-pinctrl",
1862 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) in npcm7xx_gpio_of() argument
1864 int ret = -ENXIO; in npcm7xx_gpio_of()
1870 for_each_available_child_of_node(pctrl->dev->of_node, np) in npcm7xx_gpio_of()
1871 if (of_find_property(np, "gpio-controller", NULL)) { in npcm7xx_gpio_of()
1874 dev_err(pctrl->dev, in npcm7xx_gpio_of()
1879 pctrl->gpio_bank[id].base = in npcm7xx_gpio_of()
1884 dev_err(pctrl->dev, in npcm7xx_gpio_of()
1890 ret = bgpio_init(&pctrl->gpio_bank[id].gc, in npcm7xx_gpio_of()
1891 pctrl->dev, 4, in npcm7xx_gpio_of()
1892 pctrl->gpio_bank[id].base + in npcm7xx_gpio_of()
1894 pctrl->gpio_bank[id].base + in npcm7xx_gpio_of()
1898 pctrl->gpio_bank[id].base + in npcm7xx_gpio_of()
1902 dev_err(pctrl->dev, "bgpio_init() failed\n"); in npcm7xx_gpio_of()
1907 "gpio-ranges", 3, in npcm7xx_gpio_of()
1910 dev_err(pctrl->dev, in npcm7xx_gpio_of()
1911 "gpio-ranges fail for GPIO bank %u\n", in npcm7xx_gpio_of()
1916 pctrl->gpio_bank[id].irq = irq; in npcm7xx_gpio_of()
1917 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; in npcm7xx_gpio_of()
1918 pctrl->gpio_bank[id].gc.parent = pctrl->dev; in npcm7xx_gpio_of()
1919 pctrl->gpio_bank[id].irqbase = in npcm7xx_gpio_of()
1921 pctrl->gpio_bank[id].pinctrl_id = pinspec.args[0]; in npcm7xx_gpio_of()
1922 pctrl->gpio_bank[id].gc.base = pinspec.args[1]; in npcm7xx_gpio_of()
1923 pctrl->gpio_bank[id].gc.ngpio = pinspec.args[2]; in npcm7xx_gpio_of()
1924 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; in npcm7xx_gpio_of()
1925 pctrl->gpio_bank[id].gc.label = in npcm7xx_gpio_of()
1926 devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF", in npcm7xx_gpio_of()
1928 if (pctrl->gpio_bank[id].gc.label == NULL) in npcm7xx_gpio_of()
1929 return -ENOMEM; in npcm7xx_gpio_of()
1931 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; in npcm7xx_gpio_of()
1932 pctrl->gpio_bank[id].direction_input = in npcm7xx_gpio_of()
1933 pctrl->gpio_bank[id].gc.direction_input; in npcm7xx_gpio_of()
1934 pctrl->gpio_bank[id].gc.direction_input = in npcm7xx_gpio_of()
1936 pctrl->gpio_bank[id].direction_output = in npcm7xx_gpio_of()
1937 pctrl->gpio_bank[id].gc.direction_output; in npcm7xx_gpio_of()
1938 pctrl->gpio_bank[id].gc.direction_output = in npcm7xx_gpio_of()
1940 pctrl->gpio_bank[id].request = in npcm7xx_gpio_of()
1941 pctrl->gpio_bank[id].gc.request; in npcm7xx_gpio_of()
1942 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; in npcm7xx_gpio_of()
1943 pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free; in npcm7xx_gpio_of()
1944 pctrl->gpio_bank[id].gc.of_node = np; in npcm7xx_gpio_of()
1948 pctrl->bank_num = id; in npcm7xx_gpio_of()
1952 static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) in npcm7xx_gpio_register() argument
1956 for (id = 0 ; id < pctrl->bank_num ; id++) { in npcm7xx_gpio_register()
1959 girq = &pctrl->gpio_bank[id].gc.irq; in npcm7xx_gpio_register()
1960 girq->chip = &pctrl->gpio_bank[id].irq_chip; in npcm7xx_gpio_register()
1961 girq->parent_handler = npcmgpio_irq_handler; in npcm7xx_gpio_register()
1962 girq->num_parents = 1; in npcm7xx_gpio_register()
1963 girq->parents = devm_kcalloc(pctrl->dev, 1, in npcm7xx_gpio_register()
1964 sizeof(*girq->parents), in npcm7xx_gpio_register()
1966 if (!girq->parents) { in npcm7xx_gpio_register()
1967 ret = -ENOMEM; in npcm7xx_gpio_register()
1970 girq->parents[0] = pctrl->gpio_bank[id].irq; in npcm7xx_gpio_register()
1971 girq->default_type = IRQ_TYPE_NONE; in npcm7xx_gpio_register()
1972 girq->handler = handle_level_irq; in npcm7xx_gpio_register()
1973 ret = devm_gpiochip_add_data(pctrl->dev, in npcm7xx_gpio_register()
1974 &pctrl->gpio_bank[id].gc, in npcm7xx_gpio_register()
1975 &pctrl->gpio_bank[id]); in npcm7xx_gpio_register()
1977 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); in npcm7xx_gpio_register()
1981 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc, in npcm7xx_gpio_register()
1982 dev_name(pctrl->dev), in npcm7xx_gpio_register()
1983 pctrl->gpio_bank[id].pinctrl_id, in npcm7xx_gpio_register()
1984 pctrl->gpio_bank[id].gc.base, in npcm7xx_gpio_register()
1985 pctrl->gpio_bank[id].gc.ngpio); in npcm7xx_gpio_register()
1987 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); in npcm7xx_gpio_register()
1988 gpiochip_remove(&pctrl->gpio_bank[id].gc); in npcm7xx_gpio_register()
1996 for (; id > 0; id--) in npcm7xx_gpio_register()
1997 gpiochip_remove(&pctrl->gpio_bank[id - 1].gc); in npcm7xx_gpio_register()
2004 struct npcm7xx_pinctrl *pctrl; in npcm7xx_pinctrl_probe() local
2007 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in npcm7xx_pinctrl_probe()
2008 if (!pctrl) in npcm7xx_pinctrl_probe()
2009 return -ENOMEM; in npcm7xx_pinctrl_probe()
2011 pctrl->dev = &pdev->dev; in npcm7xx_pinctrl_probe()
2012 dev_set_drvdata(&pdev->dev, pctrl); in npcm7xx_pinctrl_probe()
2014 pctrl->gcr_regmap = in npcm7xx_pinctrl_probe()
2015 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); in npcm7xx_pinctrl_probe()
2016 if (IS_ERR(pctrl->gcr_regmap)) { in npcm7xx_pinctrl_probe()
2017 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n"); in npcm7xx_pinctrl_probe()
2018 return PTR_ERR(pctrl->gcr_regmap); in npcm7xx_pinctrl_probe()
2021 ret = npcm7xx_gpio_of(pctrl); in npcm7xx_pinctrl_probe()
2023 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret); in npcm7xx_pinctrl_probe()
2027 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, in npcm7xx_pinctrl_probe()
2028 &npcm7xx_pinctrl_desc, pctrl); in npcm7xx_pinctrl_probe()
2029 if (IS_ERR(pctrl->pctldev)) { in npcm7xx_pinctrl_probe()
2030 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); in npcm7xx_pinctrl_probe()
2031 return PTR_ERR(pctrl->pctldev); in npcm7xx_pinctrl_probe()
2034 ret = npcm7xx_gpio_register(pctrl); in npcm7xx_pinctrl_probe()
2036 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret); in npcm7xx_pinctrl_probe()
2045 { .compatible = "nuvoton,npcm750-pinctrl" },
2053 .name = "npcm7xx-pinctrl",