Lines Matching full:value
264 u32 value; in tegra210_pex_uphy_enable() local
280 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
281 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
283 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
285 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
287 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
288 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
290 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
295 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
296 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
298 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
299 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
300 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
302 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
303 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
304 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
306 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
307 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_pex_uphy_enable()
311 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_pex_uphy_enable()
314 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
316 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
317 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_pex_uphy_enable()
321 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_pex_uphy_enable()
323 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
325 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
326 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_pex_uphy_enable()
327 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
329 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
330 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_pex_uphy_enable()
332 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
336 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
337 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_pex_uphy_enable()
338 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
340 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
341 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
342 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
347 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
348 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_pex_uphy_enable()
359 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
360 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
361 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
366 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
367 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_pex_uphy_enable()
378 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
379 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_pex_uphy_enable()
380 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
385 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
386 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_pex_uphy_enable()
397 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
398 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_pex_uphy_enable()
400 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
405 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
406 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_pex_uphy_enable()
417 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
418 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_pex_uphy_enable()
419 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
424 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
425 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_pex_uphy_enable()
436 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
437 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_pex_uphy_enable()
438 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
442 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
443 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
444 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
446 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
447 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
448 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
450 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
451 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
452 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
493 u32 value; in tegra210_sata_uphy_enable() local
509 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
510 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_sata_uphy_enable()
512 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_sata_uphy_enable()
514 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
516 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
517 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_sata_uphy_enable()
519 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_sata_uphy_enable()
521 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
523 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
524 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
525 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
527 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
528 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
529 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
531 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
532 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
533 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
535 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
536 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_sata_uphy_enable()
540 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; in tegra210_sata_uphy_enable()
543 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_sata_uphy_enable()
546 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL << in tegra210_sata_uphy_enable()
549 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN; in tegra210_sata_uphy_enable()
550 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
552 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
553 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_sata_uphy_enable()
559 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_sata_uphy_enable()
562 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL << in tegra210_sata_uphy_enable()
565 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
567 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
568 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_sata_uphy_enable()
569 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
571 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
572 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_sata_uphy_enable()
574 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
578 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
579 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_sata_uphy_enable()
580 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
582 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
583 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
584 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
589 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
590 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_sata_uphy_enable()
601 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
602 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
603 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
608 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
609 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_sata_uphy_enable()
620 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
621 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_sata_uphy_enable()
622 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
627 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
628 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_sata_uphy_enable()
639 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
640 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_sata_uphy_enable()
642 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
647 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
648 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_sata_uphy_enable()
659 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
660 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_sata_uphy_enable()
661 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
666 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
667 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_sata_uphy_enable()
678 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
679 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_sata_uphy_enable()
680 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
684 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
685 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
686 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
688 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
689 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
690 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
692 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
693 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
694 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
732 u32 value; in tegra210_xusb_padctl_enable() local
739 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
740 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_xusb_padctl_enable()
741 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
745 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
746 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_xusb_padctl_enable()
747 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
751 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
752 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_xusb_padctl_enable()
753 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
762 u32 value; in tegra210_xusb_padctl_disable() local
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
773 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_xusb_padctl_disable()
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
779 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_xusb_padctl_disable()
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
784 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
785 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_xusb_padctl_disable()
786 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
796 u32 value; in tegra210_hsic_set_idle() local
798 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
800 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_set_idle()
805 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
809 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
813 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
823 u32 value, offset; in tegra210_usb3_set_lfps_detect() local
836 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
838 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK << in tegra210_usb3_set_lfps_detect()
844 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL << in tegra210_usb3_set_lfps_detect()
850 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
920 u32 value; in tegra210_usb2_phy_init() local
922 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
923 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK << in tegra210_usb2_phy_init()
925 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB << in tegra210_usb2_phy_init()
927 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
942 u32 value; in tegra210_xusb_padctl_vbus_override() local
946 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
949 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; in tegra210_xusb_padctl_vbus_override()
950 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << in tegra210_xusb_padctl_vbus_override()
952 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << in tegra210_xusb_padctl_vbus_override()
955 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; in tegra210_xusb_padctl_vbus_override()
958 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
966 u32 value; in tegra210_xusb_padctl_id_override() local
970 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
973 if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) { in tegra210_xusb_padctl_id_override()
974 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; in tegra210_xusb_padctl_id_override()
975 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
978 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
981 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << in tegra210_xusb_padctl_id_override()
983 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED << in tegra210_xusb_padctl_id_override()
986 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << in tegra210_xusb_padctl_id_override()
988 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << in tegra210_xusb_padctl_id_override()
992 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1045 u32 value; in tegra210_usb2_phy_power_on() local
1057 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1058 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK( in tegra210_usb2_phy_power_on()
1060 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP( in tegra210_usb2_phy_power_on()
1062 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1064 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1065 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN( in tegra210_usb2_phy_power_on()
1067 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1071 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1072 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY( in tegra210_usb2_phy_power_on()
1074 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1078 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1079 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN( in tegra210_usb2_phy_power_on()
1081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1084 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1085 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK << in tegra210_usb2_phy_power_on()
1089 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL << in tegra210_usb2_phy_power_on()
1093 value |= in tegra210_usb2_phy_power_on()
1097 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1099 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
1100 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); in tegra210_usb2_phy_power_on()
1102 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index); in tegra210_usb2_phy_power_on()
1104 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index); in tegra210_usb2_phy_power_on()
1106 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); in tegra210_usb2_phy_power_on()
1108 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index); in tegra210_usb2_phy_power_on()
1109 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
1111 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
1112 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK << in tegra210_usb2_phy_power_on()
1117 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
1120 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
1122 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
1123 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK << in tegra210_usb2_phy_power_on()
1130 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
1134 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
1136 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
1138 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << in tegra210_usb2_phy_power_on()
1141 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; in tegra210_usb2_phy_power_on()
1143 value |= in tegra210_usb2_phy_power_on()
1146 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
1167 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1168 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << in tegra210_usb2_phy_power_on()
1172 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << in tegra210_usb2_phy_power_on()
1176 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1178 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1179 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_on()
1180 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1184 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1185 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; in tegra210_usb2_phy_power_on()
1186 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1209 u32 value; in tegra210_usb2_phy_power_off() local
1221 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1222 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY( in tegra210_usb2_phy_power_off()
1224 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1228 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1229 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN( in tegra210_usb2_phy_power_off()
1231 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1235 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1236 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN( in tegra210_usb2_phy_power_off()
1238 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1240 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
1241 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake, in tegra210_usb2_phy_power_off()
1243 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
1252 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1253 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_off()
1254 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1385 u32 value; in tegra210_hsic_phy_init() local
1387 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1388 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK << in tegra210_hsic_phy_init()
1390 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB << in tegra210_hsic_phy_init()
1392 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1411 u32 value; in tegra210_hsic_phy_power_on() local
1421 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1422 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK << in tegra210_hsic_phy_power_on()
1424 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1426 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1428 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1429 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK << in tegra210_hsic_phy_power_on()
1433 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1437 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1439 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1440 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_phy_power_on()
1452 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_phy_power_on()
1455 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1461 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1462 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK << in tegra210_hsic_phy_power_on()
1466 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL << in tegra210_hsic_phy_power_on()
1470 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1474 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1475 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK; in tegra210_hsic_phy_power_on()
1476 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1495 u32 value; in tegra210_hsic_phy_power_off() local
1497 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
1498 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | in tegra210_hsic_phy_power_off()
1507 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
1658 u32 value; in tegra210_pcie_phy_power_on() local
1667 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1669 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1680 u32 value; in tegra210_pcie_phy_power_off() local
1682 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1684 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1829 u32 value; in tegra210_sata_phy_power_on() local
1838 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1839 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1840 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1851 u32 value; in tegra210_sata_phy_power_off() local
1853 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1854 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1855 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1991 u32 value; in tegra210_usb3_port_enable() local
1994 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1997 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_port_enable()
1999 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_port_enable()
2001 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_port_enable()
2002 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
2003 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
2014 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
2015 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK << in tegra210_usb3_port_enable()
2017 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL << in tegra210_usb3_port_enable()
2019 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
2021 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
2022 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK << in tegra210_usb3_port_enable()
2024 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL << in tegra210_usb3_port_enable()
2026 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
2031 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
2032 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK << in tegra210_usb3_port_enable()
2034 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL << in tegra210_usb3_port_enable()
2036 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
2052 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2053 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_port_enable()
2054 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2058 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2059 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_port_enable()
2060 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2064 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2065 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_port_enable()
2066 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2077 u32 value; in tegra210_usb3_port_disable() local
2079 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2080 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_port_disable()
2081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2085 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2086 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_port_disable()
2087 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2091 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2092 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_port_disable()
2093 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2102 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
2103 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_port_disable()
2104 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); in tegra210_usb3_port_disable()
2105 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
2136 u32 value; in tegra210_utmi_port_reset() local
2141 value = padctl_readl(padctl, in tegra210_utmi_port_reset()
2144 if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) || in tegra210_utmi_port_reset()
2145 (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) { in tegra210_utmi_port_reset()
2158 u32 value; in tegra210_xusb_read_fuse_calibration() local
2161 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); in tegra210_xusb_read_fuse_calibration()
2167 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) & in tegra210_xusb_read_fuse_calibration()
2172 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) & in tegra210_xusb_read_fuse_calibration()
2175 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); in tegra210_xusb_read_fuse_calibration()
2180 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) & in tegra210_xusb_read_fuse_calibration()