Lines Matching +full:0 +full:x31c
22 #define SPEAR1340_PCM_CFG 0x100
24 #define SPEAR1340_PCM_WKUP_CFG 0x104
25 #define SPEAR1340_SWITCH_CTR 0x108
27 #define SPEAR1340_PERIP1_SW_RST 0x318
29 #define SPEAR1340_PERIP2_SW_RST 0x31C
30 #define SPEAR1340_PERIP3_SW_RST 0x320
33 #define SPEAR1340_PCIE_SATA_CFG 0x424
43 #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
45 #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
57 #define SPEAR1340_PCIE_MIPHY_CFG 0x428
62 #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
63 #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
80 /* phy mode: 0 for SATA 1 for PCIe */
105 SPEAR1340_PERIP1_SW_RSATA, 0); in spear1340_miphy_sata_init()
109 return 0; in spear1340_miphy_sata_init()
115 SPEAR1340_PCIE_SATA_CFG_MASK, 0); in spear1340_miphy_sata_exit()
117 SPEAR1340_PCIE_MIPHY_CFG_MASK, 0); in spear1340_miphy_sata_exit()
127 SPEAR1340_PCM_CFG_SATA_POWER_EN, 0); in spear1340_miphy_sata_exit()
131 return 0; in spear1340_miphy_sata_exit()
143 return 0; in spear1340_miphy_pcie_init()
149 SPEAR1340_PCIE_MIPHY_CFG_MASK, 0); in spear1340_miphy_pcie_exit()
151 SPEAR1340_PCIE_SATA_CFG_MASK, 0); in spear1340_miphy_pcie_exit()
153 return 0; in spear1340_miphy_pcie_exit()
159 int ret = 0; in spear1340_miphy_init()
172 int ret = 0; in spear1340_miphy_exit()
198 int ret = 0; in spear1340_miphy_suspend()
209 int ret = 0; in spear1340_miphy_resume()
231 priv->mode = args->args[0]; in spear1340_miphy_xlate()
274 return 0; in spear1340_miphy_probe()