Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
26 /* REG: 0x00 */
28 /* REG: 0x01 */
32 /* REG: 0x02 */
35 /* REG: 0x03 */
38 /* REG: 0x04 */
40 /* REG: 0xaa */
42 /* REG: 0xe0 */
49 /* REG: 0xe1 */
52 /* REG: 0xe2 */
59 /* REG: 0xe3 */
61 /* REG: 0xe4 */
67 /* REG: 0xe5 */
72 /* REG: 0xe6 */
79 /* REG: 0xe8 */
81 /* REG: 0xe9 */
85 /* REG: 0xea */
87 /* REG: 0xeb */
93 /* REG: 0xee */
95 /* REG: 0xef */
100 /* REG: 0xf0 */
107 /* REG: 0xf1 */
110 /* REG: 0xf2 */
114 /* REG: 0x01 */
118 /* REG: 0x02 */
122 /* REG:0x05 */
125 /* REG:0x07 */
128 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
133 /* REG: 0xa0 */
137 /* REG: 0xa1 */
140 /* REG: 0xa2 */
147 /* REG: 0xa3 */
149 /* REG: 0xa4*/
156 /* REG: 0xa5 */
162 /* REG: 0xa6 */
168 /* REG: 0xa9 */
170 /* REG: 0xaa */
174 /* REG:0xab */
177 /* REG: 0xac */
179 /* REG: 0xad */
184 /* REG: 0xaf */
186 /* REG: 0xb0 */
188 /* REG: 0xb2 */
197 /* REG:0xc5 */
200 /* REG:0xc6 */
202 /* REG:0xc7 */
207 /* REG 0xc8 - 0xcb */
221 /* REG: 0xd1 */
223 /* REG: 0xd2 */
225 /* REG: 0xd3 */
377 * The register description of the IP block does not use any distinct names
378 * but instead the databook simply numbers the registers in one-increments.
380 * translate the databook register names to the actual registers addresses.
382 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) in inno_write() argument
384 regmap_write(inno->regmap, reg * 4, val); in inno_write()
387 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) in inno_read() argument
391 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
396 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() argument
399 regmap_update_bits(inno->regmap, reg * 4, mask, val); in inno_update_bits()
402 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ argument
403 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
409 int bus_width = phy_get_bus_width(inno->phy); in inno_hdmi_phy_get_tmdsclk()
461 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
463 inno->pixclock); in inno_hdmi_phy_power_on()
467 dev_err(inno->dev, "TMDS clock is zero!\n"); in inno_hdmi_phy_power_on()
468 return -EINVAL; in inno_hdmi_phy_power_on()
471 if (!inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
472 return -EINVAL; in inno_hdmi_phy_power_on()
474 for (; cfg->tmdsclock != 0; cfg++) in inno_hdmi_phy_power_on()
475 if (tmdsclock <= cfg->tmdsclock && in inno_hdmi_phy_power_on()
476 cfg->version & inno->chip_version) in inno_hdmi_phy_power_on()
479 for (; phy_cfg->tmdsclock != 0; phy_cfg++) in inno_hdmi_phy_power_on()
480 if (tmdsclock <= phy_cfg->tmdsclock) in inno_hdmi_phy_power_on()
483 if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0) in inno_hdmi_phy_power_on()
484 return -EINVAL; in inno_hdmi_phy_power_on()
486 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
488 ret = clk_prepare_enable(inno->phyclk); in inno_hdmi_phy_power_on()
492 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
494 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_on()
505 if (!inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
506 return -EINVAL; in inno_hdmi_phy_power_off()
508 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
510 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_off()
512 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); in inno_hdmi_phy_power_off()
530 for (; cfg->pixclock != 0; cfg++) in inno_hdmi_phy_get_pre_pll_cfg()
531 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) in inno_hdmi_phy_get_pre_pll_cfg()
534 if (cfg->pixclock == 0) in inno_hdmi_phy_get_pre_pll_cfg()
535 return ERR_PTR(-EINVAL); in inno_hdmi_phy_get_pre_pll_cfg()
593 inno->pixclock = vco; in inno_hdmi_phy_rk3228_clk_recalc_rate()
595 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_phy_rk3228_clk_recalc_rate()
608 for (; cfg->pixclock != 0; cfg++) in inno_hdmi_phy_rk3228_clk_round_rate()
609 if (cfg->pixclock == rate && !cfg->fracdiv) in inno_hdmi_phy_rk3228_clk_round_rate()
612 if (cfg->pixclock == 0) in inno_hdmi_phy_rk3228_clk_round_rate()
613 return -EINVAL; in inno_hdmi_phy_rk3228_clk_round_rate()
615 return cfg->pixclock; in inno_hdmi_phy_rk3228_clk_round_rate()
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", in inno_hdmi_phy_rk3228_clk_set_rate()
635 /* Power down PRE-PLL */ in inno_hdmi_phy_rk3228_clk_set_rate()
642 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3228_clk_set_rate()
643 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) | in inno_hdmi_phy_rk3228_clk_set_rate()
644 RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_clk_set_rate()
645 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_clk_set_rate()
648 RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | in inno_hdmi_phy_rk3228_clk_set_rate()
649 RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a)); in inno_hdmi_phy_rk3228_clk_set_rate()
652 RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3228_clk_set_rate()
653 RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); in inno_hdmi_phy_rk3228_clk_set_rate()
657 RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3228_clk_set_rate()
658 RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | in inno_hdmi_phy_rk3228_clk_set_rate()
659 RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); in inno_hdmi_phy_rk3228_clk_set_rate()
661 /* Power up PRE-PLL */ in inno_hdmi_phy_rk3228_clk_set_rate()
664 /* Wait for Pre-PLL lock */ in inno_hdmi_phy_rk3228_clk_set_rate()
668 dev_err(inno->dev, "Pre-PLL locking failed\n"); in inno_hdmi_phy_rk3228_clk_set_rate()
672 inno->pixclock = rate; in inno_hdmi_phy_rk3228_clk_set_rate()
748 inno->pixclock = vco; in inno_hdmi_phy_rk3328_clk_recalc_rate()
749 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_phy_rk3328_clk_recalc_rate()
762 for (; cfg->pixclock != 0; cfg++) in inno_hdmi_phy_rk3328_clk_round_rate()
763 if (cfg->pixclock == rate) in inno_hdmi_phy_rk3328_clk_round_rate()
766 if (cfg->pixclock == 0) in inno_hdmi_phy_rk3328_clk_round_rate()
767 return -EINVAL; in inno_hdmi_phy_rk3328_clk_round_rate()
769 return cfg->pixclock; in inno_hdmi_phy_rk3328_clk_round_rate()
782 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", in inno_hdmi_phy_rk3328_clk_set_rate()
792 /* Configure pre-pll */ in inno_hdmi_phy_rk3328_clk_set_rate()
794 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); in inno_hdmi_phy_rk3328_clk_set_rate()
795 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_clk_set_rate()
798 if (!cfg->fracdiv) in inno_hdmi_phy_rk3328_clk_set_rate()
800 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); in inno_hdmi_phy_rk3328_clk_set_rate()
801 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
802 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | in inno_hdmi_phy_rk3328_clk_set_rate()
803 RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b)); in inno_hdmi_phy_rk3328_clk_set_rate()
804 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()
805 RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); in inno_hdmi_phy_rk3328_clk_set_rate()
806 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()
807 RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | in inno_hdmi_phy_rk3328_clk_set_rate()
808 RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); in inno_hdmi_phy_rk3328_clk_set_rate()
809 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
810 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
811 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
815 /* Wait for Pre-PLL lock */ in inno_hdmi_phy_rk3328_clk_set_rate()
819 dev_err(inno->dev, "Pre-PLL locking failed\n"); in inno_hdmi_phy_rk3328_clk_set_rate()
823 inno->pixclock = rate; in inno_hdmi_phy_rk3328_clk_set_rate()
839 struct device *dev = inno->dev; in inno_hdmi_phy_clk_register()
840 struct device_node *np = dev->of_node; in inno_hdmi_phy_clk_register()
845 parent_name = __clk_get_name(inno->refoclk); in inno_hdmi_phy_clk_register()
851 init.ops = inno->plat_data->clk_ops; in inno_hdmi_phy_clk_register()
854 of_property_read_string(np, "clock-output-names", &init.name); in inno_hdmi_phy_clk_register()
856 inno->hw.init = &init; in inno_hdmi_phy_clk_register()
858 inno->phyclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
859 if (IS_ERR(inno->phyclk)) { in inno_hdmi_phy_clk_register()
860 ret = PTR_ERR(inno->phyclk); in inno_hdmi_phy_clk_register()
865 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk); in inno_hdmi_phy_clk_register()
886 /* manual power down post-PLL */ in inno_hdmi_phy_rk3228_init()
890 inno->chip_version = 1; in inno_hdmi_phy_rk3228_init()
910 /* Post-PLL update */ in inno_hdmi_phy_rk3228_power_on()
912 RK3228_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_power_on()
914 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
915 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
917 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
921 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
930 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
943 dev_err(inno->dev, "Post-PLL locking failed\n"); in inno_hdmi_phy_rk3228_power_on()
947 if (cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3228_power_on()
988 /* try to read the chip-version */ in inno_hdmi_phy_rk3328_init()
989 inno->chip_version = 1; in inno_hdmi_phy_rk3328_init()
990 cell = nvmem_cell_get(inno->dev, "cpu-version"); in inno_hdmi_phy_rk3328_init()
992 if (PTR_ERR(cell) == -EPROBE_DEFER) in inno_hdmi_phy_rk3328_init()
993 return -EPROBE_DEFER; in inno_hdmi_phy_rk3328_init()
1004 inno->chip_version = efuse_buf[0] + 1; in inno_hdmi_phy_rk3328_init()
1022 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_power_on()
1023 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1025 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
1026 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
1028 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
1031 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
1032 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
1038 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3328_power_on()
1045 if (phy_cfg->tmdsclock > 340000000) { in inno_hdmi_phy_rk3328_power_on()
1047 v = clk_get_rate(inno->sysclk) / 100000; in inno_hdmi_phy_rk3328_power_on()
1058 if (phy_cfg->tmdsclock > 165000000) in inno_hdmi_phy_rk3328_power_on()
1081 dev_err(inno->dev, "Post-PLL locking failed\n"); in inno_hdmi_phy_rk3328_power_on()
1085 if (phy_cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3328_power_on()
1139 clk_disable_unprepare(inno->refpclk); in inno_hdmi_phy_action()
1140 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_action()
1151 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL); in inno_hdmi_phy_probe()
1153 return -ENOMEM; in inno_hdmi_phy_probe()
1155 inno->dev = &pdev->dev; in inno_hdmi_phy_probe()
1157 inno->plat_data = of_device_get_match_data(inno->dev); in inno_hdmi_phy_probe()
1158 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_probe()
1159 return -EINVAL; in inno_hdmi_phy_probe()
1162 regs = devm_ioremap_resource(inno->dev, res); in inno_hdmi_phy_probe()
1166 inno->sysclk = devm_clk_get(inno->dev, "sysclk"); in inno_hdmi_phy_probe()
1167 if (IS_ERR(inno->sysclk)) { in inno_hdmi_phy_probe()
1168 ret = PTR_ERR(inno->sysclk); in inno_hdmi_phy_probe()
1169 dev_err(inno->dev, "failed to get sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1173 inno->refpclk = devm_clk_get(inno->dev, "refpclk"); in inno_hdmi_phy_probe()
1174 if (IS_ERR(inno->refpclk)) { in inno_hdmi_phy_probe()
1175 ret = PTR_ERR(inno->refpclk); in inno_hdmi_phy_probe()
1176 dev_err(inno->dev, "failed to get ref clock: %d\n", ret); in inno_hdmi_phy_probe()
1180 inno->refoclk = devm_clk_get(inno->dev, "refoclk"); in inno_hdmi_phy_probe()
1181 if (IS_ERR(inno->refoclk)) { in inno_hdmi_phy_probe()
1182 ret = PTR_ERR(inno->refoclk); in inno_hdmi_phy_probe()
1183 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n", in inno_hdmi_phy_probe()
1188 ret = clk_prepare_enable(inno->sysclk); in inno_hdmi_phy_probe()
1190 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1198 ret = clk_prepare_enable(inno->refpclk); in inno_hdmi_phy_probe()
1200 dev_err(inno->dev, "failed to enable refpclk\n"); in inno_hdmi_phy_probe()
1201 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_probe()
1205 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action, in inno_hdmi_phy_probe()
1210 inno->regmap = devm_regmap_init_mmio(inno->dev, regs, in inno_hdmi_phy_probe()
1212 if (IS_ERR(inno->regmap)) in inno_hdmi_phy_probe()
1213 return PTR_ERR(inno->regmap); in inno_hdmi_phy_probe()
1216 inno->irq = platform_get_irq(pdev, 0); in inno_hdmi_phy_probe()
1217 if (inno->irq > 0) { in inno_hdmi_phy_probe()
1218 ret = devm_request_threaded_irq(inno->dev, inno->irq, in inno_hdmi_phy_probe()
1222 dev_name(inno->dev), inno); in inno_hdmi_phy_probe()
1227 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops); in inno_hdmi_phy_probe()
1228 if (IS_ERR(inno->phy)) { in inno_hdmi_phy_probe()
1229 dev_err(inno->dev, "failed to create HDMI PHY\n"); in inno_hdmi_phy_probe()
1230 return PTR_ERR(inno->phy); in inno_hdmi_phy_probe()
1233 phy_set_drvdata(inno->phy, inno); in inno_hdmi_phy_probe()
1234 phy_set_bus_width(inno->phy, 8); in inno_hdmi_phy_probe()
1236 if (inno->plat_data->ops->init) { in inno_hdmi_phy_probe()
1237 ret = inno->plat_data->ops->init(inno); in inno_hdmi_phy_probe()
1246 phy_provider = devm_of_phy_provider_register(inno->dev, in inno_hdmi_phy_probe()
1253 of_clk_del_provider(pdev->dev.of_node); in inno_hdmi_phy_remove()
1260 .compatible = "rockchip,rk3228-hdmi-phy",
1263 .compatible = "rockchip,rk3328-hdmi-phy",
1273 .name = "inno-hdmi-phy",
1279 MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");