28  * indirectly from the SDS offset at 0x2000. It is only required for
30  * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
31  * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
36  * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
52 #define SERDES_PLL_INDIRECT_OFFSET	0x0000
53 #define SERDES_PLL_REF_INDIRECT_OFFSET	0x2000
54 #define SERDES_INDIRECT_OFFSET		0x0400
55 #define SERDES_LANE_STRIDE		0x0200
58 #define DEFAULT_SATA_TXBOOST_GAIN	{ 0x1e, 0x1e, 0x1e }
59 #define DEFAULT_SATA_TXEYEDIRECTION	{ 0x0, 0x0, 0x0 }
60 #define DEFAULT_SATA_TXEYETUNING	{ 0xa, 0xa, 0xa }
61 #define DEFAULT_SATA_SPD_SEL		{ 0x1, 0x3, 0x7 }
62 #define DEFAULT_SATA_TXAMP		{ 0x8, 0x8, 0x8 }
63 #define DEFAULT_SATA_TXCN1		{ 0x2, 0x2, 0x2 }
64 #define DEFAULT_SATA_TXCN2		{ 0x0, 0x0, 0x0 }
65 #define DEFAULT_SATA_TXCP1		{ 0xa, 0xa, 0xa }
67 #define SATA_SPD_SEL_GEN3		0x7
68 #define SATA_SPD_SEL_GEN2		0x3
69 #define SATA_SPD_SEL_GEN1		0x1
71 #define SSC_DISABLE			0
74 #define FBDIV_VAL_50M			0x77
75 #define REFDIV_VAL_50M			0x1
76 #define FBDIV_VAL_100M			0x3B
77 #define REFDIV_VAL_100M			0x0
80 #define SATACLKENREG			0x00000000
81 #define  SATA0_CORE_CLKEN		0x00000002
82 #define  SATA1_CORE_CLKEN		0x00000004
83 #define SATASRESETREG			0x00000004
84 #define  SATA_MEM_RESET_MASK		0x00000020
85 #define  SATA_MEM_RESET_RD(src)		(((src) & 0x00000020) >> 5)
86 #define  SATA_SDS_RESET_MASK		0x00000004
87 #define  SATA_CSR_RESET_MASK		0x00000001
88 #define  SATA_CORE_RESET_MASK		0x00000002
89 #define  SATA_PMCLK_RESET_MASK		0x00000010
90 #define  SATA_PCLK_RESET_MASK		0x00000008
93 #define SATA_ENET_SDS_PCS_CTL0		0x00000000
95 		(((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
97 		(((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
98 #define SATA_ENET_SDS_CTL0		0x0000000c
100 		(((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
101 #define SATA_ENET_SDS_CTL1		0x00000010
103 		(((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
104 #define SATA_ENET_SDS_RST_CTL		0x00000024
105 #define SATA_ENET_SDS_IND_CMD_REG	0x0000003c
106 #define  CFG_IND_WR_CMD_MASK		0x00000001
107 #define  CFG_IND_RD_CMD_MASK		0x00000002
108 #define  CFG_IND_CMD_DONE_MASK		0x00000004
110 		(((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
111 #define SATA_ENET_SDS_IND_RDATA_REG	0x00000040
112 #define SATA_ENET_SDS_IND_WDATA_REG	0x00000044
113 #define SATA_ENET_CLK_MACRO_REG		0x0000004c
115 		(((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
117 		(((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
119 		(((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
120 #define  O_PLL_LOCK_RD(src)		(((src) & 0x40000000) >> 30)
121 #define  O_PLL_READY_RD(src)		(((src) & 0x80000000) >> 31)
124 #define CMU_REG0			0x00000
125 #define  CMU_REG0_PLL_REF_SEL_MASK	0x00002000
127 		(((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
128 #define  CMU_REG0_PDOWN_MASK		0x00004000
130 		(((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
131 #define CMU_REG1			0x00002
133 		(((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
135 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
137 		(((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
138 #define  CMU_REG1_REFCLK_CMOS_SEL_MASK	0x00000001
140 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
141 #define CMU_REG2			0x00004
143 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
145 		(((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
147 		(((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
148 #define CMU_REG3			0x00006
150 		(((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
152 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
154 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
155 #define CMU_REG4			0x00008
156 #define CMU_REG5			0x0000a
158 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
160 		(((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
162 		(((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
163 #define  CMU_REG5_PLL_RESETB_MASK	0x00000001
164 #define CMU_REG6			0x0000c
166 		(((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
168 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
169 #define CMU_REG7			0x0000e
170 #define  CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14)
171 #define  CMU_REG7_VCO_CAL_FAIL_RD(src)	((0x00000c00 & (u32) (src)) >> 10)
172 #define CMU_REG8			0x00010
173 #define CMU_REG9			0x00012
174 #define  CMU_REG9_WORD_LEN_8BIT		0x000
175 #define  CMU_REG9_WORD_LEN_10BIT	0x001
176 #define  CMU_REG9_WORD_LEN_16BIT	0x002
177 #define  CMU_REG9_WORD_LEN_20BIT	0x003
178 #define  CMU_REG9_WORD_LEN_32BIT	0x004
179 #define  CMU_REG9_WORD_LEN_40BIT	0x005
180 #define  CMU_REG9_WORD_LEN_64BIT	0x006
181 #define  CMU_REG9_WORD_LEN_66BIT	0x007
183 		(((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
185 		(((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
187 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
189 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
191 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
192 #define CMU_REG10			0x00014
194 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
195 #define CMU_REG11			0x00016
196 #define CMU_REG12			0x00018
198 		(((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
199 #define CMU_REG13			0x0001a
200 #define CMU_REG14			0x0001c
201 #define CMU_REG15			0x0001e
202 #define CMU_REG16			0x00020
203 #define  CMU_REG16_PVT_DN_MAN_ENA_MASK	0x00000001
204 #define  CMU_REG16_PVT_UP_MAN_ENA_MASK	0x00000002
206 		(((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
208 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
210 		(((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
211 #define CMU_REG17			0x00022
213 		(((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
215 		(((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
216 #define  CMU_REG17_PVT_TERM_MAN_ENA_MASK	0x00008000
217 #define CMU_REG18			0x00024
218 #define CMU_REG19			0x00026
219 #define CMU_REG20			0x00028
220 #define CMU_REG21			0x0002a
221 #define CMU_REG22			0x0002c
222 #define CMU_REG23			0x0002e
223 #define CMU_REG24			0x00030
224 #define CMU_REG25			0x00032
225 #define CMU_REG26			0x00034
227 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
228 #define CMU_REG27			0x00036
229 #define CMU_REG28			0x00038
230 #define CMU_REG29			0x0003a
231 #define CMU_REG30			0x0003c
233 		(((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
235 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
236 #define CMU_REG31			0x0003e
237 #define CMU_REG32			0x00040
238 #define  CMU_REG32_FORCE_VCOCAL_START_MASK	0x00004000
240 		(((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
242 		(((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
243 #define CMU_REG33			0x00042
244 #define CMU_REG34			0x00044
246 		(((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
248 		(((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
250 		(((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
252 		(((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
253 #define CMU_REG35			0x00046
255 		(((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
256 #define CMU_REG36				0x00048
258 		(((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
260 		(((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
262 		(((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
263 #define CMU_REG37			0x0004a
264 #define CMU_REG38			0x0004c
265 #define CMU_REG39			0x0004e
268 #define RXTX_REG0			0x000
270 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
272 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
274 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
275 #define RXTX_REG1			0x002
277 		(((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
279 		(((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
281 		(((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
283 		(((dst) & ~0x00000006) | (((u32) (src) << 1) &  0x00000006))
284 #define RXTX_REG2			0x004
286 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
288 		(((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
290 		(((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
291 #define RXTX_REG4			0x008
292 #define  RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK	0x00000040
294 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
296 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
297 #define RXTX_REG5			0x00a
299 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
301 		(((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
303 		(((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
304 #define RXTX_REG6			0x00c
306 		(((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
308 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
310 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
312 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
314 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
315 #define RXTX_REG7			0x00e
316 #define  RXTX_REG7_RESETB_RXD_MASK	0x00000100
317 #define  RXTX_REG7_RESETB_RXA_MASK	0x00000080
319 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
321 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
322 #define RXTX_REG8			0x010
324 		(((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
326 		(((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
328 		(((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
330 		(((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
332 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
333 #define RXTX_REG7			0x00e
335 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
337 		(((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
338 #define  RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK	0x00004000
340 		(((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
341 #define RXTX_REG11			0x016
343 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
344 #define RXTX_REG12			0x018
346 		(((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
348 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
349 #define  RXTX_REG12_RX_DET_TERM_ENABLE_MASK	0x00000002
351 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
352 #define RXTX_REG13			0x01a
353 #define RXTX_REG14			0x01c
355 		(((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
357 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
358 #define RXTX_REG26			0x034
360 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
362 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
363 #define RXTX_REG21			0x02a
364 #define  RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
365 #define  RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
366 #define  RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src)	((0x0000000f & (u32)(src)))
367 #define RXTX_REG22			0x02c
368 #define  RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
369 #define  RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
370 #define  RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src)	((0x0000000f & (u32)(src)))
371 #define RXTX_REG23			0x02e
372 #define  RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
373 #define  RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
374 #define RXTX_REG24			0x030
375 #define  RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
376 #define  RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
377 #define RXTX_REG27			0x036
378 #define RXTX_REG28			0x038
379 #define RXTX_REG31			0x03e
380 #define RXTX_REG38			0x04c
382 		(((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
383 #define RXTX_REG39			0x04e
384 #define RXTX_REG40			0x050
385 #define RXTX_REG41			0x052
386 #define RXTX_REG42			0x054
387 #define RXTX_REG43			0x056
388 #define RXTX_REG44			0x058
389 #define RXTX_REG45			0x05a
390 #define RXTX_REG46			0x05c
391 #define RXTX_REG47			0x05e
392 #define RXTX_REG48			0x060
393 #define RXTX_REG49			0x062
394 #define RXTX_REG50			0x064
395 #define RXTX_REG51			0x066
396 #define RXTX_REG52			0x068
397 #define RXTX_REG53			0x06a
398 #define RXTX_REG54			0x06c
399 #define RXTX_REG55			0x06e
400 #define RXTX_REG61			0x07a
402 		(((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
404 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
406 		(((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
408 		(((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
409 #define RXTX_REG62			0x07c
411 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
412 #define RXTX_REG81			0x0a2
414 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
416 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
418 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
419 #define RXTX_REG96			0x0c0
421 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
423 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
425 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
426 #define RXTX_REG99			0x0c6
428 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
430 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
432 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
433 #define RXTX_REG102			0x0cc
435 		(((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
436 #define RXTX_REG114			0x0e4
437 #define RXTX_REG121			0x0f2
438 #define  RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1)
439 #define RXTX_REG125			0x0fa
441 		(((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
443 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
445 		(((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
447 		(((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
449 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
450 #define RXTX_REG127			0x0fe
451 #define  RXTX_REG127_FORCE_SUM_CAL_START_MASK	0x00000002
452 #define  RXTX_REG127_FORCE_LAT_CAL_START_MASK	0x00000004
454 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
456 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
458 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
460 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
462 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
463 #define RXTX_REG128			0x100
465 		(((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
467 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
469 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
470 #define RXTX_REG129			0x102
472 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
474 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
475 #define RXTX_REG130			0x104
477 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
479 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
480 #define RXTX_REG145			0x122
482 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
484 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
486 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
488 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
489 #define RXTX_REG147			0x126
490 #define RXTX_REG148			0x128
494 	REF_CMU = 0,	/* Clock macro is the internal reference clock */
499 	MUX_SELECT_ATA = 0,	/* Switch the MUX to ATA */
500 	MUX_SELECT_SGMMII = 0,	/* Switch the MUX to SGMII */
504 	CLK_EXT_DIFF = 0,	/* External differential */
510 	MODE_SATA	= 0,	/* List them for simple reference */
547 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
568 		pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",  in sds_wr()
589 		pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",  in sds_rd()
607 	pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);  in cmu_wr()
621 	pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data);  in cmu_rd()
668 	pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data,  in serdes_wr()
680 	pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data);  in serdes_rd()
711 	val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
714 	cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222);  in xgene_phy_cfg_cmu_clk_type()
715 	cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225);  in xgene_phy_cfg_cmu_clk_type()
721 		val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
725 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
731 		val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
735 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
746 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
750 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
767 		val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
768 		val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);  in xgene_phy_sata_cfg_cmu_core()
769 		val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
770 		val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);  in xgene_phy_sata_cfg_cmu_core()
777 		val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
779 		val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
784 	val = CMU_REG1_PLL_CP_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
786 		val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);  in xgene_phy_sata_cfg_cmu_core()
788 		val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
790 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
792 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
801 		val = CMU_REG2_PLL_LFRES_SET(val, 0xa);  in xgene_phy_sata_cfg_cmu_core()
804 		val = CMU_REG2_PLL_LFRES_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
806 			ref_100MHz = 0;  in xgene_phy_sata_cfg_cmu_core()
822 		val = CMU_REG3_VCOVARSEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
823 		val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);  in xgene_phy_sata_cfg_cmu_core()
825 		val = CMU_REG3_VCOVARSEL_SET(val, 0xF);  in xgene_phy_sata_cfg_cmu_core()
827 			val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);  in xgene_phy_sata_cfg_cmu_core()
829 			val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);  in xgene_phy_sata_cfg_cmu_core()
830 		val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);  in xgene_phy_sata_cfg_cmu_core()
836 	val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
841 	val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
842 	val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
844 		val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
846 		val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
851 	val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);  in xgene_phy_sata_cfg_cmu_core()
852 	val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);  in xgene_phy_sata_cfg_cmu_core()
862 		val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
864 			val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
865 			val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);  in xgene_phy_sata_cfg_cmu_core()
871 			val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
877 	val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
878 	val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
880 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
882 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
887 	val = CMU_REG30_PCIE_MODE_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
888 	val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
892 	cmu_wr(ctx, cmu_type, CMU_REG31, 0xF);  in xgene_phy_sata_cfg_cmu_core()
895 	val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
897 		val = CMU_REG32_IREF_ADJ_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
899 		val = CMU_REG32_IREF_ADJ_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
904 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27);  in xgene_phy_sata_cfg_cmu_core()
906 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c);  in xgene_phy_sata_cfg_cmu_core()
909 	cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F);  in xgene_phy_sata_cfg_cmu_core()
945 	for (lane = 0; lane < MAX_LANE; lane++) {  in xgene_phy_sata_cfg_lanes()
946 		serdes_wr(ctx, lane, RXTX_REG147, 0x6);  in xgene_phy_sata_cfg_lanes()
950 		val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
951 		val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
952 		val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
957 		val = RXTX_REG1_RXACVCM_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
966 		val = RXTX_REG2_VTT_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
967 		val = RXTX_REG2_VTT_SEL_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
968 		val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
978 			val = RXTX_REG1_RXVREG1_SET(val, 0x2);  in xgene_phy_sata_cfg_lanes()
979 			val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);  in xgene_phy_sata_cfg_lanes()
1001 		val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1002 		val = RXTX_REG6_TX_IDLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1003 		val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1004 		val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1009 		val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1015 		val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1016 		val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1017 		val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1018 		val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1019 		val = RXTX_REG8_SD_VREF_SET(val, 0x4);  in xgene_phy_sata_cfg_lanes()
1024 		val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1029 		val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1030 		val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1031 		val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1036 		val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1037 		val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1040 		serdes_wr(ctx, lane, RXTX_REG28, 0x0);  in xgene_phy_sata_cfg_lanes()
1043 		serdes_wr(ctx, lane, RXTX_REG31, 0x0);  in xgene_phy_sata_cfg_lanes()
1047 		val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1048 		val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1049 		val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1053 		val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1057 		for (i = 0; i < 9; i++) {  in xgene_phy_sata_cfg_lanes()
1060 			val = RXTX_REG89_MU_TH7_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1061 			val = RXTX_REG89_MU_TH8_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1062 			val = RXTX_REG89_MU_TH9_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1067 		for (i = 0; i < 3; i++) {  in xgene_phy_sata_cfg_lanes()
1070 			val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1071 			val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1072 			val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1077 		for (i = 0; i < 3; i++) {  in xgene_phy_sata_cfg_lanes()
1080 			val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1081 			val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1082 			val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1087 		val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1090 		serdes_wr(ctx, lane, RXTX_REG114, 0xffe0);  in xgene_phy_sata_cfg_lanes()
1099 		val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1103 		val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1107 		val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_lanes()
1111 		val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);  in xgene_phy_sata_cfg_lanes()
1112 		val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1114 			val = RXTX_REG145_RXES_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1115 			val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1117 			val = RXTX_REG145_RXES_ENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1118 			val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1126 		for (i = 0; i < 4; i++) {  in xgene_phy_sata_cfg_lanes()
1128 			serdes_wr(ctx, lane, reg, 0xFFFF);  in xgene_phy_sata_cfg_lanes()
1142 	writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL);  in xgene_phy_cal_rdy_chk()
1154 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1180 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);  in xgene_phy_cal_rdy_chk()
1181 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1191 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);  in xgene_phy_cal_rdy_chk()
1192 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1198 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);  in xgene_phy_cal_rdy_chk()
1199 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1216 	} while (--loop > 0);  in xgene_phy_cal_rdy_chk()
1229 	dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");  in xgene_phy_cal_rdy_chk()
1230 	return 0;  in xgene_phy_cal_rdy_chk()
1242 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);  in xgene_phy_pdwn_force_vco()
1261 	writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL);  in xgene_phy_hw_init_sata()
1264 	writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL);  in xgene_phy_hw_init_sata()
1267 	writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL);  in xgene_phy_hw_init_sata()
1273 		ctx->sata_param.txspeed[ctx->sata_param.speed[0]]);  in xgene_phy_hw_init_sata()
1278 	val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);  in xgene_phy_hw_init_sata()
1296 	val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);  in xgene_phy_hw_init_sata()
1297 	val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);  in xgene_phy_hw_init_sata()
1307 	} while (--i > 0);  in xgene_phy_hw_init_sata()
1309 	if (i <= 0)  in xgene_phy_hw_init_sata()
1312 	return 0;  in xgene_phy_hw_init_sata()
1333 	return 0;  in xgene_phy_hw_initialize()
1349 		{RXTX_REG38, 0x0},  in xgene_phy_force_lat_summer_cal()
1350 		{RXTX_REG39, 0xff00},  in xgene_phy_force_lat_summer_cal()
1351 		{RXTX_REG40, 0xffff},  in xgene_phy_force_lat_summer_cal()
1352 		{RXTX_REG41, 0xffff},  in xgene_phy_force_lat_summer_cal()
1353 		{RXTX_REG42, 0xffff},  in xgene_phy_force_lat_summer_cal()
1354 		{RXTX_REG43, 0xffff},  in xgene_phy_force_lat_summer_cal()
1355 		{RXTX_REG44, 0xffff},  in xgene_phy_force_lat_summer_cal()
1356 		{RXTX_REG45, 0xffff},  in xgene_phy_force_lat_summer_cal()
1357 		{RXTX_REG46, 0xffff},  in xgene_phy_force_lat_summer_cal()
1358 		{RXTX_REG47, 0xfffc},  in xgene_phy_force_lat_summer_cal()
1359 		{RXTX_REG48, 0x0},  in xgene_phy_force_lat_summer_cal()
1360 		{RXTX_REG49, 0x0},  in xgene_phy_force_lat_summer_cal()
1361 		{RXTX_REG50, 0x0},  in xgene_phy_force_lat_summer_cal()
1362 		{RXTX_REG51, 0x0},  in xgene_phy_force_lat_summer_cal()
1363 		{RXTX_REG52, 0x0},  in xgene_phy_force_lat_summer_cal()
1364 		{RXTX_REG53, 0x0},  in xgene_phy_force_lat_summer_cal()
1365 		{RXTX_REG54, 0x0},  in xgene_phy_force_lat_summer_cal()
1366 		{RXTX_REG55, 0x0},  in xgene_phy_force_lat_summer_cal()
1397 	serdes_wr(ctx, lane, RXTX_REG28, 0x7);  in xgene_phy_force_lat_summer_cal()
1398 	serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);  in xgene_phy_force_lat_summer_cal()
1403 	for (i = 0; i < ARRAY_SIZE(serdes_reg); i++)  in xgene_phy_force_lat_summer_cal()
1425 	int avg_loop = 0;  in xgene_phy_gen_avg_val()
1426 	int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0;  in xgene_phy_gen_avg_val()
1427 	int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0;  in xgene_phy_gen_avg_val()
1428 	int sum_cal = 0;  in xgene_phy_gen_avg_val()
1443 	serdes_wr(ctx, lane, RXTX_REG28, 0x0000);  in xgene_phy_gen_avg_val()
1445 	serdes_wr(ctx, lane, RXTX_REG31, 0x0000);  in xgene_phy_gen_avg_val()
1480 		if ((fail_even == 0 || fail_even == 1) &&  in xgene_phy_gen_avg_val()
1481 		    (fail_odd == 0 || fail_odd == 1)) {  in xgene_phy_gen_avg_val()
1493 			dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",  in xgene_phy_gen_avg_val()
1496 			dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",  in xgene_phy_gen_avg_val()
1499 			dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr);  in xgene_phy_gen_avg_val()
1545 	dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",  in xgene_phy_gen_avg_val()
1550 	dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",  in xgene_phy_gen_avg_val()
1555 	dev_dbg(ctx->dev, "SUM 0x%x\n",  in xgene_phy_gen_avg_val()
1559 	val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);  in xgene_phy_gen_avg_val()
1564 	val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);  in xgene_phy_gen_avg_val()
1570 	val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);  in xgene_phy_gen_avg_val()
1573 	serdes_wr(ctx, lane, RXTX_REG28, 0x0007);  in xgene_phy_gen_avg_val()
1575 	serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);  in xgene_phy_gen_avg_val()
1599 	for (i = 0; i < MAX_LANE; i++)  in xgene_phy_hw_init()
1603 	return 0;  in xgene_phy_hw_init()
1616 	if (args->args_count <= 0)  in xgene_phy_xlate()
1618 	if (args->args[0] >= MODE_MAX)  in xgene_phy_xlate()
1621 	ctx->mode = args->args[0];  in xgene_phy_xlate()
1634 		for (i = 0; i < count; i++)  in xgene_phy_get_param()
1639 	for (i = 0; i < count; i++)  in xgene_phy_get_param()
1664 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in xgene_phy_probe()
1689 	for (i = 0; i < MAX_LANE; i++)  in xgene_phy_probe()