Lines Matching +full:combophy +full:- +full:lgm
1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
55 * for ComboPhy according to the mode.
63 /* ComboPhy mode Register values */
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
120 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_pcie_refclk_cfg()
121 u32 mask = BIT(cbphy->id * 2 + iphy->id); in intel_cbphy_pcie_refclk_cfg()
127 return regmap_update_bits(cbphy->syscfg, PAD_DIS_CFG, mask, val); in intel_cbphy_pcie_refclk_cfg()
144 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_cfg()
151 if (cbphy->aggr_mode != PHY_DL_MODE) in intel_cbphy_iphy_cfg()
154 return phy_cfg(&cbphy->iphy[PHY_1]); in intel_cbphy_iphy_cfg()
159 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_pcie_en_pad_refclk()
164 dev_err(cbphy->dev, "Failed to enable PCIe pad refclk\n"); in intel_cbphy_pcie_en_pad_refclk()
168 if (cbphy->init_cnt) in intel_cbphy_pcie_en_pad_refclk()
171 combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL, in intel_cbphy_pcie_en_pad_refclk()
182 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_pcie_dis_pad_refclk()
187 dev_err(cbphy->dev, "Failed to disable PCIe pad refclk\n"); in intel_cbphy_pcie_dis_pad_refclk()
191 if (cbphy->init_cnt) in intel_cbphy_pcie_dis_pad_refclk()
194 combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL, in intel_cbphy_pcie_dis_pad_refclk()
203 enum aggregated_mode aggr = cbphy->aggr_mode; in intel_cbphy_set_mode()
204 struct device *dev = cbphy->dev; in intel_cbphy_set_mode()
208 mode = cbphy->phy_mode; in intel_cbphy_set_mode()
222 return -EINVAL; in intel_cbphy_set_mode()
228 return -EINVAL; in intel_cbphy_set_mode()
231 ret = regmap_write(cbphy->hsiocfg, REG_COMBO_MODE(cbphy->bid), cb_mode); in intel_cbphy_set_mode()
233 dev_err(dev, "Failed to set ComboPhy mode: %d\n", ret); in intel_cbphy_set_mode()
240 reset_control_assert(cbphy->core_rst); in intel_cbphy_rst_assert()
241 reset_control_assert(cbphy->phy_rst); in intel_cbphy_rst_assert()
246 reset_control_deassert(cbphy->core_rst); in intel_cbphy_rst_deassert()
247 reset_control_deassert(cbphy->phy_rst); in intel_cbphy_rst_deassert()
254 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_power_on()
257 if (!cbphy->init_cnt) { in intel_cbphy_iphy_power_on()
258 ret = clk_prepare_enable(cbphy->core_clk); in intel_cbphy_iphy_power_on()
260 dev_err(cbphy->dev, "Clock enable failed!\n"); in intel_cbphy_iphy_power_on()
264 ret = clk_set_rate(cbphy->core_clk, cbphy->clk_rate); in intel_cbphy_iphy_power_on()
266 dev_err(cbphy->dev, "Clock freq set to %lu failed!\n", in intel_cbphy_iphy_power_on()
267 cbphy->clk_rate); in intel_cbphy_iphy_power_on()
280 dev_err(cbphy->dev, "Failed enabling PHY core\n"); in intel_cbphy_iphy_power_on()
284 ret = reset_control_deassert(iphy->app_rst); in intel_cbphy_iphy_power_on()
286 dev_err(cbphy->dev, "PHY(%u:%u) reset deassert failed!\n", in intel_cbphy_iphy_power_on()
297 clk_disable_unprepare(cbphy->core_clk); in intel_cbphy_iphy_power_on()
304 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_power_off()
307 ret = reset_control_assert(iphy->app_rst); in intel_cbphy_iphy_power_off()
309 dev_err(cbphy->dev, "PHY(%u:%u) reset assert failed!\n", in intel_cbphy_iphy_power_off()
316 dev_err(cbphy->dev, "Failed disabling PHY core\n"); in intel_cbphy_iphy_power_off()
320 if (cbphy->init_cnt) in intel_cbphy_iphy_power_off()
323 clk_disable_unprepare(cbphy->core_clk); in intel_cbphy_iphy_power_off()
332 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_init()
335 mutex_lock(&cbphy->lock); in intel_cbphy_init()
340 if (cbphy->phy_mode == PHY_PCIE_MODE) { in intel_cbphy_init()
346 cbphy->init_cnt++; in intel_cbphy_init()
349 mutex_unlock(&cbphy->lock); in intel_cbphy_init()
357 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_exit()
360 mutex_lock(&cbphy->lock); in intel_cbphy_exit()
361 cbphy->init_cnt--; in intel_cbphy_exit()
362 if (cbphy->phy_mode == PHY_PCIE_MODE) { in intel_cbphy_exit()
371 mutex_unlock(&cbphy->lock); in intel_cbphy_exit()
379 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_calibrate()
380 void __iomem *cr_base = cbphy->cr_base; in intel_cbphy_calibrate()
383 if (cbphy->phy_mode != PHY_XPCS_MODE) in intel_cbphy_calibrate()
395 dev_err(cbphy->dev, "RX Adaptation failed!\n"); in intel_cbphy_calibrate()
397 dev_dbg(cbphy->dev, "RX Adaptation success!\n"); in intel_cbphy_calibrate()
408 struct device *dev = cbphy->dev; in intel_cbphy_fwnode_parse()
415 cbphy->core_clk = devm_clk_get(dev, NULL); in intel_cbphy_fwnode_parse()
416 if (IS_ERR(cbphy->core_clk)) { in intel_cbphy_fwnode_parse()
417 ret = PTR_ERR(cbphy->core_clk); in intel_cbphy_fwnode_parse()
418 if (ret != -EPROBE_DEFER) in intel_cbphy_fwnode_parse()
423 cbphy->core_rst = devm_reset_control_get_optional(dev, "core"); in intel_cbphy_fwnode_parse()
424 if (IS_ERR(cbphy->core_rst)) { in intel_cbphy_fwnode_parse()
425 ret = PTR_ERR(cbphy->core_rst); in intel_cbphy_fwnode_parse()
426 if (ret != -EPROBE_DEFER) in intel_cbphy_fwnode_parse()
431 cbphy->phy_rst = devm_reset_control_get_optional(dev, "phy"); in intel_cbphy_fwnode_parse()
432 if (IS_ERR(cbphy->phy_rst)) { in intel_cbphy_fwnode_parse()
433 ret = PTR_ERR(cbphy->phy_rst); in intel_cbphy_fwnode_parse()
434 if (ret != -EPROBE_DEFER) in intel_cbphy_fwnode_parse()
439 cbphy->iphy[0].app_rst = devm_reset_control_get_optional(dev, "iphy0"); in intel_cbphy_fwnode_parse()
440 if (IS_ERR(cbphy->iphy[0].app_rst)) { in intel_cbphy_fwnode_parse()
441 ret = PTR_ERR(cbphy->iphy[0].app_rst); in intel_cbphy_fwnode_parse()
442 if (ret != -EPROBE_DEFER) in intel_cbphy_fwnode_parse()
447 cbphy->iphy[1].app_rst = devm_reset_control_get_optional(dev, "iphy1"); in intel_cbphy_fwnode_parse()
448 if (IS_ERR(cbphy->iphy[1].app_rst)) { in intel_cbphy_fwnode_parse()
449 ret = PTR_ERR(cbphy->iphy[1].app_rst); in intel_cbphy_fwnode_parse()
450 if (ret != -EPROBE_DEFER) in intel_cbphy_fwnode_parse()
455 cbphy->app_base = devm_platform_ioremap_resource_byname(pdev, "app"); in intel_cbphy_fwnode_parse()
456 if (IS_ERR(cbphy->app_base)) in intel_cbphy_fwnode_parse()
457 return PTR_ERR(cbphy->app_base); in intel_cbphy_fwnode_parse()
459 cbphy->cr_base = devm_platform_ioremap_resource_byname(pdev, "core"); in intel_cbphy_fwnode_parse()
460 if (IS_ERR(cbphy->cr_base)) in intel_cbphy_fwnode_parse()
461 return PTR_ERR(cbphy->cr_base); in intel_cbphy_fwnode_parse()
465 * in which ComboPhy subsytem specific registers are subset. Using in intel_cbphy_fwnode_parse()
473 cbphy->id = ref.args[0]; in intel_cbphy_fwnode_parse()
474 cbphy->syscfg = device_node_to_regmap(to_of_node(ref.fwnode)); in intel_cbphy_fwnode_parse()
482 cbphy->bid = ref.args[0]; in intel_cbphy_fwnode_parse()
483 cbphy->hsiocfg = device_node_to_regmap(to_of_node(ref.fwnode)); in intel_cbphy_fwnode_parse()
486 ret = fwnode_property_read_u32_array(fwnode, "intel,phy-mode", &val, 1); in intel_cbphy_fwnode_parse()
492 cbphy->phy_mode = PHY_PCIE_MODE; in intel_cbphy_fwnode_parse()
496 cbphy->phy_mode = PHY_SATA_MODE; in intel_cbphy_fwnode_parse()
500 cbphy->phy_mode = PHY_XPCS_MODE; in intel_cbphy_fwnode_parse()
505 return -EINVAL; in intel_cbphy_fwnode_parse()
508 cbphy->clk_rate = intel_iphy_clk_rates[cbphy->phy_mode]; in intel_cbphy_fwnode_parse()
511 cbphy->aggr_mode = PHY_DL_MODE; in intel_cbphy_fwnode_parse()
513 cbphy->aggr_mode = PHY_SL_MODE; in intel_cbphy_fwnode_parse()
531 if (args->args_count < 1) { in intel_cbphy_xlate()
533 return ERR_PTR(-EINVAL); in intel_cbphy_xlate()
536 iphy_id = args->args[0]; in intel_cbphy_xlate()
539 return ERR_PTR(-EINVAL); in intel_cbphy_xlate()
542 if (cbphy->aggr_mode == PHY_DL_MODE && iphy_id == PHY_1) { in intel_cbphy_xlate()
543 dev_err(dev, "Invalid. ComboPhy is in Dual lane mode %d\n", iphy_id); in intel_cbphy_xlate()
544 return ERR_PTR(-EINVAL); in intel_cbphy_xlate()
547 return cbphy->iphy[iphy_id].phy; in intel_cbphy_xlate()
553 struct device *dev = cbphy->dev; in intel_cbphy_create()
558 iphy = &cbphy->iphy[i]; in intel_cbphy_create()
559 iphy->parent = cbphy; in intel_cbphy_create()
560 iphy->id = i; in intel_cbphy_create()
563 if (cbphy->aggr_mode == PHY_DL_MODE && iphy->id == PHY_1) in intel_cbphy_create()
566 iphy->phy = devm_phy_create(dev, NULL, &intel_cbphy_ops); in intel_cbphy_create()
567 if (IS_ERR(iphy->phy)) { in intel_cbphy_create()
571 return PTR_ERR(iphy->phy); in intel_cbphy_create()
574 phy_set_drvdata(iphy->phy, iphy); in intel_cbphy_create()
587 struct device *dev = &pdev->dev; in intel_cbphy_probe()
593 return -ENOMEM; in intel_cbphy_probe()
595 cbphy->dev = dev; in intel_cbphy_probe()
596 cbphy->init_cnt = 0; in intel_cbphy_probe()
597 mutex_init(&cbphy->lock); in intel_cbphy_probe()
612 clk_disable_unprepare(cbphy->core_clk); in intel_cbphy_remove()
617 { .compatible = "intel,combo-phy" },
618 { .compatible = "intel,combophy-lgm" },
626 .name = "intel-combo-phy",
633 MODULE_DESCRIPTION("Intel Combo-phy driver");