Lines Matching +full:ddr +full:- +full:pmu

1 # SPDX-License-Identifier: GPL-2.0-only
10 	tristate "ARM CCI PMU driver"
14 	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 	  If compiled as a module, it will be called arm-cci.
20 	bool "support CCI-400"
25 	  CCI-400 provides 4 independent event counters counting events related
29 	bool "support CCI-500/CCI-550"
33 	  CCI-500/CCI-550 both provide 8 independent event counters, which can
41 	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 	tristate "Arm CMN-600 PMU support"
48 	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
53 	bool "ARM PMU framework"
56 	  Say y if you want to use CPU performance monitors on ARM-based
73 	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
78 	  system, control logic. The PMU allows counting various events related
82 	tristate "Freescale i.MX8 DDR perf monitor"
85 	  Provides support for the DDR performance monitor in i.MX8, which
90 	bool "Qualcomm Technologies L2-cache PMU"
94 	  Provides support for the L2 cache performance monitor unit (PMU)
96 	  Adds the L2 cache PMU into the perf events subsystem for
100 	bool "Qualcomm Technologies L3-cache PMU"
104 	   Provides support for the L3 cache performance monitor unit (PMU)
106 	   Adds the L3 cache PMU into the perf events subsystem for
110 	tristate "Cavium ThunderX2 SoC PMU UNCORE"
115 	   The SoC has PMU support in its L3 cache controller (L3C) and
120         bool "APM X-Gene SoC PMU"
123           Say y if you want to use APM X-Gene SoC performance monitors.