Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
51 if (r->domain_nr == domain_nr) in get_pci_domain_busn_res()
52 return &r->res; in get_pci_domain_busn_res()
58 r->domain_nr = domain_nr; in get_pci_domain_busn_res()
59 r->res.start = 0; in get_pci_domain_busn_res()
60 r->res.end = 0xff; in get_pci_domain_busn_res()
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; in get_pci_domain_busn_res()
63 list_add_tail(&r->list, &pci_domain_busn_res_list); in get_pci_domain_busn_res()
65 return &r->res; in get_pci_domain_busn_res()
92 put_device(pci_bus->bridge); in release_pcibus_dev()
120 size = size & ~(size-1); in pci_size()
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) in pci_size()
153 /* 1M mem BAR treated as 32-bit BAR */ in decode_bar()
159 /* mem unknown type treated as 32-bit BAR */ in decode_bar()
168 * pci_read_base - Read a PCI BAR
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
187 if (!dev->mmio_always_on) { in __pci_read_base()
195 res->name = pci_name(dev); in __pci_read_base()
219 res->flags = decode_bar(dev, l); in __pci_read_base()
220 res->flags |= IORESOURCE_SIZEALIGN; in __pci_read_base()
221 if (res->flags & IORESOURCE_IO) { in __pci_read_base()
232 res->flags |= IORESOURCE_ROM_ENABLE; in __pci_read_base()
238 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", in __pci_read_base()
262 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; in __pci_read_base()
266 res->start = 0; in __pci_read_base()
267 res->end = 0; in __pci_read_base()
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", in __pci_read_base()
274 /* Above 32-bit boundary; try to reallocate */ in __pci_read_base()
275 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
276 res->start = 0; in __pci_read_base()
277 res->end = sz64 - 1; in __pci_read_base()
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", in __pci_read_base()
285 region.end = l64 + sz64 - 1; in __pci_read_base()
287 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
302 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
303 res->start = 0; in __pci_read_base()
304 res->end = region.end - region.start; in __pci_read_base()
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", in __pci_read_base()
313 res->flags = 0; in __pci_read_base()
315 if (res->flags) in __pci_read_base()
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res); in __pci_read_base()
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; in __pci_read_base()
323 unsigned int pos, reg; in pci_read_bases() local
325 if (dev->non_compliant_bars) in pci_read_bases()
329 if (dev->is_virtfn) in pci_read_bases()
333 struct resource *res = &dev->resource[pos]; in pci_read_bases()
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); in pci_read_bases()
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); in pci_read_bases()
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
340 dev->rom_base_reg = rom; in pci_read_bases()
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | in pci_read_bases()
359 bridge->io_window = 1; in pci_read_bridge_windows()
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) in pci_read_bridge_windows()
379 bridge->pref_window = 1; in pci_read_bridge_windows()
384 * Bridge claims to have a 64-bit prefetchable memory in pci_read_bridge_windows()
394 bridge->pref_64_window = 1; in pci_read_bridge_windows()
400 struct pci_dev *dev = child->self; in pci_read_bridge_io()
408 if (dev->io_window_1k) { in pci_read_bridge_io()
414 res = child->resource[0]; in pci_read_bridge_io()
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; in pci_read_bridge_io()
432 region.end = limit + io_granularity - 1; in pci_read_bridge_io()
433 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
440 struct pci_dev *dev = child->self; in pci_read_bridge_mmio()
446 res = child->resource[1]; in pci_read_bridge_mmio()
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; in pci_read_bridge_mmio()
455 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
462 struct pci_dev *dev = child->self; in pci_read_bridge_mmio_pref()
469 res = child->resource[2]; in pci_read_bridge_mmio_pref()
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | in pci_read_bridge_mmio_pref()
504 if (res->flags & PCI_PREF_RANGE_TYPE_64) in pci_read_bridge_mmio_pref()
505 res->flags |= IORESOURCE_MEM_64; in pci_read_bridge_mmio_pref()
508 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
515 struct pci_dev *dev = child->self; in pci_read_bridge_bases()
523 &child->busn_res, in pci_read_bridge_bases()
524 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
534 if (dev->transparent) { in pci_read_bridge_bases()
535 pci_bus_for_each_resource(child->parent, res, i) { in pci_read_bridge_bases()
536 if (res && res->flags) { in pci_read_bridge_bases()
554 INIT_LIST_HEAD(&b->node); in pci_alloc_bus()
555 INIT_LIST_HEAD(&b->children); in pci_alloc_bus()
556 INIT_LIST_HEAD(&b->devices); in pci_alloc_bus()
557 INIT_LIST_HEAD(&b->slots); in pci_alloc_bus()
558 INIT_LIST_HEAD(&b->resources); in pci_alloc_bus()
559 b->max_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
563 b->domain_nr = parent->domain_nr; in pci_alloc_bus()
572 if (bridge->release_fn) in pci_release_host_bridge_dev()
573 bridge->release_fn(bridge); in pci_release_host_bridge_dev()
575 pci_free_resource_list(&bridge->windows); in pci_release_host_bridge_dev()
576 pci_free_resource_list(&bridge->dma_ranges); in pci_release_host_bridge_dev()
582 INIT_LIST_HEAD(&bridge->windows); in pci_init_host_bridge()
583 INIT_LIST_HEAD(&bridge->dma_ranges); in pci_init_host_bridge()
591 bridge->native_aer = 1; in pci_init_host_bridge()
592 bridge->native_pcie_hotplug = 1; in pci_init_host_bridge()
593 bridge->native_shpc_hotplug = 1; in pci_init_host_bridge()
594 bridge->native_pme = 1; in pci_init_host_bridge()
595 bridge->native_ltr = 1; in pci_init_host_bridge()
596 bridge->native_dpc = 1; in pci_init_host_bridge()
598 device_initialize(&bridge->dev); in pci_init_host_bridge()
610 bridge->dev.release = pci_release_host_bridge_dev; in pci_alloc_host_bridge()
631 bridge->dev.parent = dev; in devm_pci_alloc_host_bridge()
648 put_device(&bridge->dev); in pci_free_host_bridge()
699 "66 MHz PCI-X", /* 0x02 */ in pci_speed_string()
700 "100 MHz PCI-X", /* 0x03 */ in pci_speed_string()
701 "133 MHz PCI-X", /* 0x04 */ in pci_speed_string()
706 "66 MHz PCI-X 266", /* 0x09 */ in pci_speed_string()
707 "100 MHz PCI-X 266", /* 0x0a */ in pci_speed_string()
708 "133 MHz PCI-X 266", /* 0x0b */ in pci_speed_string()
714 "66 MHz PCI-X 533", /* 0x11 */ in pci_speed_string()
715 "100 MHz PCI-X 533", /* 0x12 */ in pci_speed_string()
716 "133 MHz PCI-X 533", /* 0x13 */ in pci_speed_string()
732 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; in pcie_update_link_speed()
769 struct pci_dev *bridge = bus->self; in pci_set_bus_speed()
779 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); in pci_set_bus_speed()
782 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); in pci_set_bus_speed()
806 bus->max_bus_speed = max; in pci_set_bus_speed()
807 bus->cur_bus_speed = pcix_bus_speed[ in pci_set_bus_speed()
818 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; in pci_set_bus_speed()
819 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); in pci_set_bus_speed()
862 * created by an SR-IOV device. Walk up to the first bridge device in pci_set_bus_msi_domain()
865 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { in pci_set_bus_msi_domain()
866 if (b->self) in pci_set_bus_msi_domain()
867 d = dev_get_msi_domain(&b->self->dev); in pci_set_bus_msi_domain()
873 dev_set_msi_domain(&bus->dev, d); in pci_set_bus_msi_domain()
878 struct device *parent = bridge->dev.parent; in pci_register_host_bridge()
890 return -ENOMEM; in pci_register_host_bridge()
892 bridge->bus = bus; in pci_register_host_bridge()
895 list_splice_init(&bridge->windows, &resources); in pci_register_host_bridge()
896 bus->sysdata = bridge->sysdata; in pci_register_host_bridge()
897 bus->msi = bridge->msi; in pci_register_host_bridge()
898 bus->ops = bridge->ops; in pci_register_host_bridge()
899 bus->number = bus->busn_res.start = bridge->busnr; in pci_register_host_bridge()
901 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); in pci_register_host_bridge()
904 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); in pci_register_host_bridge()
907 dev_dbg(&b->dev, "bus already known\n"); in pci_register_host_bridge()
908 err = -EEXIST; in pci_register_host_bridge()
912 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), in pci_register_host_bridge()
913 bridge->busnr); in pci_register_host_bridge()
919 err = device_add(&bridge->dev); in pci_register_host_bridge()
921 put_device(&bridge->dev); in pci_register_host_bridge()
924 bus->bridge = get_device(&bridge->dev); in pci_register_host_bridge()
925 device_enable_async_suspend(bus->bridge); in pci_register_host_bridge()
930 set_dev_node(bus->bridge, pcibus_to_node(bus)); in pci_register_host_bridge()
932 bus->dev.class = &pcibus_class; in pci_register_host_bridge()
933 bus->dev.parent = bus->bridge; in pci_register_host_bridge()
935 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); in pci_register_host_bridge()
936 name = dev_name(&bus->dev); in pci_register_host_bridge()
938 err = device_register(&bus->dev); in pci_register_host_bridge()
944 if (bus->ops->add_bus) { in pci_register_host_bridge()
945 err = bus->ops->add_bus(bus); in pci_register_host_bridge()
947 dev_err(&bus->dev, "failed to add bus: %d\n", err); in pci_register_host_bridge()
959 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); in pci_register_host_bridge()
963 list_move_tail(&window->node, &bridge->windows); in pci_register_host_bridge()
964 offset = window->offset; in pci_register_host_bridge()
965 res = window->res; in pci_register_host_bridge()
967 if (res->flags & IORESOURCE_BUS) in pci_register_host_bridge()
968 pci_bus_insert_busn_res(bus, bus->number, res->end); in pci_register_host_bridge()
974 fmt = " (bus address [%#06llx-%#06llx])"; in pci_register_host_bridge()
976 fmt = " (bus address [%#010llx-%#010llx])"; in pci_register_host_bridge()
979 (unsigned long long)(res->start - offset), in pci_register_host_bridge()
980 (unsigned long long)(res->end - offset)); in pci_register_host_bridge()
984 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); in pci_register_host_bridge()
988 list_add_tail(&bus->node, &pci_root_buses); in pci_register_host_bridge()
994 put_device(&bridge->dev); in pci_register_host_bridge()
995 device_del(&bridge->dev); in pci_register_host_bridge()
1011 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_bridge_child_ext_cfg_accessible()
1027 * - PCI-to-PCI bridges in pci_bridge_child_ext_cfg_accessible()
1028 * - PCIe-to-PCI/PCI-X forward bridges in pci_bridge_child_ext_cfg_accessible()
1029 * - PCI/PCI-X-to-PCIe reverse bridges in pci_bridge_child_ext_cfg_accessible()
1031 * if the bridge supports PCI-X Mode 2. in pci_bridge_child_ext_cfg_accessible()
1054 child->parent = parent; in pci_alloc_child_bus()
1055 child->msi = parent->msi; in pci_alloc_child_bus()
1056 child->sysdata = parent->sysdata; in pci_alloc_child_bus()
1057 child->bus_flags = parent->bus_flags; in pci_alloc_child_bus()
1060 if (host->child_ops) in pci_alloc_child_bus()
1061 child->ops = host->child_ops; in pci_alloc_child_bus()
1063 child->ops = parent->ops; in pci_alloc_child_bus()
1069 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
1070 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
1073 child->number = child->busn_res.start = busnr; in pci_alloc_child_bus()
1074 child->primary = parent->busn_res.start; in pci_alloc_child_bus()
1075 child->busn_res.end = 0xff; in pci_alloc_child_bus()
1078 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
1082 child->self = bridge; in pci_alloc_child_bus()
1083 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
1084 child->dev.parent = child->bridge; in pci_alloc_child_bus()
1094 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; in pci_alloc_child_bus()
1098 /* Set up default resource pointers and names */ in pci_alloc_child_bus()
1100 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; in pci_alloc_child_bus()
1101 child->resource[i]->name = child->name; in pci_alloc_child_bus()
1103 bridge->subordinate = child; in pci_alloc_child_bus()
1107 ret = device_register(&child->dev); in pci_alloc_child_bus()
1112 if (child->ops->add_bus) { in pci_alloc_child_bus()
1113 ret = child->ops->add_bus(child); in pci_alloc_child_bus()
1115 dev_err(&child->dev, "failed to add bus: %d\n", ret); in pci_alloc_child_bus()
1132 list_add_tail(&child->node, &parent->children); in pci_add_new_bus()
1153 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1169 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) in pci_ea_fixed_busnrs()
1190 * pci_scan_bridge_extend() - Scan buses behind a bridge
1197 * distributed equally between hotplug-capable bridges.
1205 * We need to process bridges in two passes -- first we scan those
1217 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge_extend()
1230 pm_runtime_get_sync(&dev->dev); in pci_scan_bridge_extend()
1237 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge_extend()
1240 if (!primary && (primary != bus->number) && secondary && subordinate) { in pci_scan_bridge_extend()
1242 primary = bus->number; in pci_scan_bridge_extend()
1247 (primary != bus->number || secondary <= bus->number || in pci_scan_bridge_extend()
1249 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge_extend()
1255 * Disable Master-Abort Mode during probing to avoid reporting of in pci_scan_bridge_extend()
1286 child->primary = primary; in pci_scan_bridge_extend()
1288 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1296 /* Subordinate should equal child->busn_res.end */ in pci_scan_bridge_extend()
1333 * This can happen when a bridge is hot-plugged, so in this in pci_scan_bridge_extend()
1334 * case we only re-scan this bus. in pci_scan_bridge_extend()
1342 bus->busn_res.end); in pci_scan_bridge_extend()
1346 available_buses--; in pci_scan_bridge_extend()
1349 | ((unsigned int)(child->primary) << 0) in pci_scan_bridge_extend()
1350 | ((unsigned int)(child->busn_res.start) << 8) in pci_scan_bridge_extend()
1351 | ((unsigned int)(child->busn_res.end) << 16); in pci_scan_bridge_extend()
1366 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1372 * cards with a PCI-to-PCI bridge can be inserted in pci_scan_bridge_extend()
1380 while (parent->parent) { in pci_scan_bridge_extend()
1382 (parent->busn_res.end > max) && in pci_scan_bridge_extend()
1383 (parent->busn_res.end <= max+i)) { in pci_scan_bridge_extend()
1386 parent = parent->parent; in pci_scan_bridge_extend()
1392 * bridges -- try to leave one in pci_scan_bridge_extend()
1413 sprintf(child->name, in pci_scan_bridge_extend()
1415 pci_domain_nr(bus), child->number); in pci_scan_bridge_extend()
1418 while (bus->parent) { in pci_scan_bridge_extend()
1419 if ((child->busn_res.end > bus->busn_res.end) || in pci_scan_bridge_extend()
1420 (child->number > bus->busn_res.end) || in pci_scan_bridge_extend()
1421 (child->number < bus->number) || in pci_scan_bridge_extend()
1422 (child->busn_res.end < bus->number)) { in pci_scan_bridge_extend()
1423 …dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", in pci_scan_bridge_extend()
1424 &child->busn_res); in pci_scan_bridge_extend()
1427 bus = bus->parent; in pci_scan_bridge_extend()
1433 pm_runtime_put(&dev->dev); in pci_scan_bridge_extend()
1439 * pci_scan_bridge() - Scan buses behind a bridge
1450 * We need to process bridges in two passes -- first we scan those
1465 * The architecture-dependent code can tweak these, of course.
1472 if (dev->is_virtfn) { in pci_read_irq()
1473 dev->pin = 0; in pci_read_irq()
1474 dev->irq = 0; in pci_read_irq()
1479 dev->pin = irq; in pci_read_irq()
1482 dev->irq = irq; in pci_read_irq()
1496 pdev->pcie_cap = pos; in set_pcie_port_type()
1498 pdev->pcie_flags_reg = reg16; in set_pcie_port_type()
1500 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in set_pcie_port_type()
1520 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1521 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; in set_pcie_port_type()
1531 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1532 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; in set_pcie_port_type()
1543 pdev->is_hotplug_bridge = 1; in set_pcie_hotplug_bridge()
1556 if (dev->vendor == PCI_VENDOR_ID_INTEL && in set_pcie_thunderbolt()
1558 dev->is_thunderbolt = 1; in set_pcie_thunderbolt()
1573 if (parent && (parent->untrusted || parent->external_facing)) in set_pcie_untrusted()
1574 dev->untrusted = true; in set_pcie_untrusted()
1578 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1581 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1590 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1615 * pci_cfg_space_size - Get the configuration space size of the PCI device
1618 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1646 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to in pci_cfg_space_size()
1650 * the fact that the SR-IOV capability on the PF resides in extended in pci_cfg_space_size()
1651 * config space and must be accessible and non-aliased to have enabled in pci_cfg_space_size()
1655 if (dev->is_virtfn) in pci_cfg_space_size()
1659 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_cfg_space_size()
1662 class = dev->class >> 8; in pci_cfg_space_size()
1685 if (dev->is_virtfn) in pci_class()
1686 return dev->physfn->sriov->class; in pci_class()
1695 if (dev->is_virtfn) { in pci_subsystem_ids()
1696 *vendor = dev->physfn->sriov->subsystem_vendor; in pci_subsystem_ids()
1697 *device = dev->physfn->sriov->subsystem_device; in pci_subsystem_ids()
1710 if (dev->is_virtfn) in pci_hdr_type()
1711 return dev->physfn->sriov->hdr_type; in pci_hdr_type()
1726 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); in pci_msi_setup_pci_dev()
1727 if (dev->msi_cap) in pci_msi_setup_pci_dev()
1730 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); in pci_msi_setup_pci_dev()
1731 if (dev->msix_cap) in pci_msi_setup_pci_dev()
1736 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1740 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1754 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI in pci_intx_mask_broken()
1778 * pci_setup_device - Fill in class and map information of a device
1782 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1798 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1799 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1800 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1801 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1802 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1803 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1809 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) in pci_setup_device()
1812 dev->dma_mask = 0xffffffff; in pci_setup_device()
1814 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1815 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1816 PCI_FUNC(dev->devfn)); in pci_setup_device()
1820 dev->revision = class & 0xff; in pci_setup_device()
1821 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1826 /* Need to have dev->class ready */ in pci_setup_device()
1827 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1829 /* Need to have dev->cfg_size ready */ in pci_setup_device()
1835 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1841 dev->vendor, dev->device, dev->hdr_type, dev->class); in pci_setup_device()
1844 class = dev->class >> 8; in pci_setup_device()
1846 if (dev->non_compliant_bars && !dev->mmio_always_on) { in pci_setup_device()
1849 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1856 dev->broken_intx_masking = pci_intx_mask_broken(dev); in pci_setup_device()
1858 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1865 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); in pci_setup_device()
1870 * addresses. These are not always echoed in BAR0-3, and in pci_setup_device()
1871 * BAR0-3 in a few cases contain junk! in pci_setup_device()
1879 res = &dev->resource[0]; in pci_setup_device()
1880 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1881 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1882 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", in pci_setup_device()
1886 res = &dev->resource[1]; in pci_setup_device()
1887 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1888 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1889 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", in pci_setup_device()
1895 res = &dev->resource[2]; in pci_setup_device()
1896 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1897 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1898 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", in pci_setup_device()
1902 res = &dev->resource[3]; in pci_setup_device()
1903 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1904 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1905 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", in pci_setup_device()
1913 * The PCI-to-PCI bridge spec requires that subtractive in pci_setup_device()
1918 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
1924 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1925 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
1934 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1935 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
1940 dev->hdr_type); in pci_setup_device()
1941 return -EIO; in pci_setup_device()
1945 dev->class, dev->hdr_type); in pci_setup_device()
1946 dev->class = PCI_CLASS_NOT_DEFINED << 8; in pci_setup_device()
1961 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ in pci_configure_mps()
1962 if (dev->is_virtfn) in pci_configure_mps()
1973 mps = 128 << dev->pcie_mpss; in pci_configure_mps()
2004 mpss = 128 << dev->pcie_mpss; in pci_configure_mps()
2008 mpss, p_mps, 128 << bridge->pcie_mpss); in pci_configure_mps()
2044 host = pci_find_host_bridge(dev->bus); in pci_configure_extended_tags()
2052 if (host->no_ext_tags) { in pci_configure_extended_tags()
2070 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2090 if (dev->is_virtfn) in pci_configure_relaxed_ordering()
2098 * Ports. Peer-to-Peer DMA is another can of worms. in pci_configure_relaxed_ordering()
2104 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { in pci_configure_relaxed_ordering()
2114 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); in pci_configure_ltr()
2122 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); in pci_configure_ltr()
2131 dev->ltr_path = 1; in pci_configure_ltr()
2136 if (bridge && bridge->ltr_path) in pci_configure_ltr()
2137 dev->ltr_path = 1; in pci_configure_ltr()
2142 if (!host->native_ltr) in pci_configure_ltr()
2152 bridge->ltr_path)) { in pci_configure_ltr()
2155 dev->ltr_path = 1; in pci_configure_ltr()
2177 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2180 if (bridge && bridge->eetlp_prefix_path) in pci_configure_eetlp_prefix()
2181 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2190 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_configure_serr()
2225 * pci_release_dev - Free a PCI device structure when all users of it are
2240 pci_bus_put(pci_dev->bus); in pci_release_dev()
2241 kfree(pci_dev->driver_override); in pci_release_dev()
2242 bitmap_free(pci_dev->dma_alias_mask); in pci_release_dev()
2254 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
2255 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
2256 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
2286 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2287 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2293 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2294 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2305 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2306 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2332 struct pci_dev *bridge = bus->self; in pci_bus_read_dev_vendor_id()
2338 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && in pci_bus_read_dev_vendor_id()
2339 bridge->device == 0x80b5) in pci_bus_read_dev_vendor_id()
2348 * Read the config data for a PCI device, sanity-check it,
2363 dev->devfn = devfn; in pci_scan_device()
2364 dev->vendor = l & 0xffff; in pci_scan_device()
2365 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
2370 pci_bus_put(dev->bus); in pci_scan_device()
2389 /* Multi-function PCIe devices share the same link/status */ in pcie_report_downtraining()
2390 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) in pcie_report_downtraining()
2401 /* Setup MSI caps & disable MSI/MSI-X interrupts */ in pci_init_capabilities()
2404 /* Buffers for saving PCIe and PCI-X capabilities */ in pci_init_capabilities()
2409 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ in pci_init_capabilities()
2422 dev->reset_fn = 1; in pci_init_capabilities()
2428 * per-device basis should be called from here.
2438 d = dev_get_msi_domain(&dev->dev); in pci_dev_msi_domain()
2459 * device-specific MSI domain, then inherit the default domain in pci_set_msi_domain()
2464 d = dev_get_msi_domain(&dev->bus->dev); in pci_set_msi_domain()
2466 dev_set_msi_domain(&dev->dev, d); in pci_set_msi_domain()
2475 device_initialize(&dev->dev); in pci_device_add()
2476 dev->dev.release = pci_release_dev; in pci_device_add()
2478 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
2479 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
2480 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
2481 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
2483 dma_set_max_seg_size(&dev->dev, 65536); in pci_device_add()
2484 dma_set_seg_boundary(&dev->dev, 0xffffffff); in pci_device_add()
2491 dev->state_saved = false; in pci_device_add()
2500 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
2510 dev->match_driver = false; in pci_device_add()
2511 ret = device_add(&dev->dev); in pci_device_add()
2556 /* dev may be NULL for non-contiguous multifunction devices */ in next_fn()
2557 if (!dev || dev->multifunction) in next_fn()
2565 struct pci_dev *bridge = bus->self; in only_one_child()
2586 * pci_scan_slot - Scan a PCI slot on a bus for devices
2591 * discovered devices to the @bus->devices list. New devices
2615 dev->multifunction = 1; in pci_scan_slot()
2620 if (bus->self && nr) in pci_scan_slot()
2621 pcie_aspm_init_link_state(bus->self); in pci_scan_slot()
2636 * drivers attached. A hot-added device might support only the minimum in pcie_find_smpss()
2638 * where devices may be hot-added, we limit the fabric MPS to 128 so in pcie_find_smpss()
2639 * hot-added devices will work correctly. in pcie_find_smpss()
2641 * However, if we hot-add a device to a slot directly below a Root in pcie_find_smpss()
2644 * reconfigure MPS on both the Root Port and the hot-added device, in pcie_find_smpss()
2647 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. in pcie_find_smpss()
2649 if (dev->is_hotplug_bridge && in pcie_find_smpss()
2653 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
2654 *smpss = dev->pcie_mpss; in pcie_find_smpss()
2664 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
2667 dev->bus->self) in pcie_write_mps()
2682 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
2746 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
2753 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2761 if (!bus->self) in pcie_bus_configure_settings()
2764 if (!pci_is_pcie(bus->self)) in pcie_bus_configure_settings()
2768 * FIXME - Peer to peer DMA is possible, though the endpoint would need in pcie_bus_configure_settings()
2776 smpss = bus->self->pcie_mpss; in pcie_bus_configure_settings()
2778 pcie_find_smpss(bus->self, &smpss); in pcie_bus_configure_settings()
2782 pcie_bus_configure_set(bus->self, &smpss); in pcie_bus_configure_settings()
2797 * pci_scan_child_bus_extend() - Scan devices below a bus
2805 * equally between hotplug-capable bridges to allow future extension of the
2812 unsigned int start = bus->busn_res.start; in pci_scan_child_bus_extend()
2817 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus_extend()
2825 * multi-function device to a guest without passing function 0. in pci_scan_child_bus_extend()
2832 dev->multifunction = 1; in pci_scan_child_bus_extend()
2837 /* Reserve buses for SR-IOV capability */ in pci_scan_child_bus_extend()
2842 * After performing arch-dependent fixup of the bus, look behind in pci_scan_child_bus_extend()
2843 * all PCI-to-PCI bridges on this bus. in pci_scan_child_bus_extend()
2845 if (!bus->is_added) { in pci_scan_child_bus_extend()
2846 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus_extend()
2848 bus->is_added = 1; in pci_scan_child_bus_extend()
2857 if (dev->is_hotplug_bridge) in pci_scan_child_bus_extend()
2877 if (cmax - max > 1) in pci_scan_child_bus_extend()
2878 used_buses += cmax - max - 1; in pci_scan_child_bus_extend()
2894 } else if (dev->is_hotplug_bridge) { in pci_scan_child_bus_extend()
2901 buses = min(buses, available_buses - used_buses + 1); in pci_scan_child_bus_extend()
2907 if (max - cmax > 1) in pci_scan_child_bus_extend()
2908 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
2916 if (bus->self && bus->self->is_hotplug_bridge) { in pci_scan_child_bus_extend()
2918 pci_hotplug_bus_size - 1); in pci_scan_child_bus_extend()
2919 if (max - start < used_buses) { in pci_scan_child_bus_extend()
2923 if (max > bus->busn_res.end) in pci_scan_child_bus_extend()
2924 max = bus->busn_res.end; in pci_scan_child_bus_extend()
2926 dev_dbg(&bus->dev, "%pR extended by %#02x\n", in pci_scan_child_bus_extend()
2927 &bus->busn_res, max - start); in pci_scan_child_bus_extend()
2936 * Return how far we've got finding sub-buses. in pci_scan_child_bus_extend()
2938 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus_extend()
2943 * pci_scan_child_bus() - Scan devices below a bus
2956 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2959 * Default empty implementation. Replace with an architecture-specific setup
2985 bridge->dev.parent = parent; in pci_create_root_bus()
2987 list_splice_init(resources, &bridge->windows); in pci_create_root_bus()
2988 bridge->sysdata = sysdata; in pci_create_root_bus()
2989 bridge->busnr = bus; in pci_create_root_bus()
2990 bridge->ops = ops; in pci_create_root_bus()
2996 return bridge->bus; in pci_create_root_bus()
2999 put_device(&bridge->dev); in pci_create_root_bus()
3011 dev_err(bridge->dev.parent, "Scanning root bridge failed"); in pci_host_probe()
3015 bus = bridge->bus; in pci_host_probe()
3028 list_for_each_entry(child, &bus->children, node) in pci_host_probe()
3039 struct resource *res = &b->busn_res; in pci_bus_insert_busn_res()
3042 res->start = bus; in pci_bus_insert_busn_res()
3043 res->end = bus_max; in pci_bus_insert_busn_res()
3044 res->flags = IORESOURCE_BUS; in pci_bus_insert_busn_res()
3047 parent_res = &b->parent->busn_res; in pci_bus_insert_busn_res()
3050 res->flags |= IORESOURCE_PCI_FIXED; in pci_bus_insert_busn_res()
3056 dev_info(&b->dev, in pci_bus_insert_busn_res()
3059 parent_res, conflict->name, conflict); in pci_bus_insert_busn_res()
3066 struct resource *res = &b->busn_res; in pci_bus_update_busn_res_end()
3071 if (res->start > bus_max) in pci_bus_update_busn_res_end()
3072 return -EINVAL; in pci_bus_update_busn_res_end()
3074 size = bus_max - res->start + 1; in pci_bus_update_busn_res_end()
3075 ret = adjust_resource(res, res->start, size); in pci_bus_update_busn_res_end()
3076 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", in pci_bus_update_busn_res_end()
3079 if (!ret && !res->parent) in pci_bus_update_busn_res_end()
3080 pci_bus_insert_busn_res(b, res->start, res->end); in pci_bus_update_busn_res_end()
3087 struct resource *res = &b->busn_res; in pci_bus_release_busn_res()
3090 if (!res->flags || !res->parent) in pci_bus_release_busn_res()
3094 dev_info(&b->dev, "busn_res: %pR %s released\n", in pci_bus_release_busn_res()
3106 return -EINVAL; in pci_scan_root_bus_bridge()
3108 resource_list_for_each_entry(window, &bridge->windows) in pci_scan_root_bus_bridge()
3109 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus_bridge()
3110 bridge->busnr = window->res->start; in pci_scan_root_bus_bridge()
3119 b = bridge->bus; in pci_scan_root_bus_bridge()
3120 bus = bridge->busnr; in pci_scan_root_bus_bridge()
3123 dev_info(&b->dev, in pci_scan_root_bus_bridge()
3124 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus_bridge()
3147 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus()
3157 dev_info(&b->dev, in pci_scan_root_bus()
3158 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus()
3192 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3205 struct pci_bus *bus = bridge->subordinate; in pci_rescan_bus_bridge_resize()
3217 * pci_rescan_bus - Scan a PCI bus for devices
3261 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; in pci_sort_bf_cmp()
3262 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; in pci_sort_bf_cmp()
3264 if (a->bus->number < b->bus->number) return -1; in pci_sort_bf_cmp()
3265 else if (a->bus->number > b->bus->number) return 1; in pci_sort_bf_cmp()
3267 if (a->devfn < b->devfn) return -1; in pci_sort_bf_cmp()
3268 else if (a->devfn > b->devfn) return 1; in pci_sort_bf_cmp()
3280 struct pci_bus *parent = dev->bus; in pci_hp_add_bridge()
3281 int busnr, start = parent->busn_res.start; in pci_hp_add_bridge()
3283 int end = parent->busn_res.end; in pci_hp_add_bridge()
3289 if (busnr-- > end) { in pci_hp_add_bridge()
3290 pci_err(dev, "No bus number available for hot-added bridge\n"); in pci_hp_add_bridge()
3291 return -1; in pci_hp_add_bridge()
3298 * Distribute the available bus numbers between hotplug-capable in pci_hp_add_bridge()
3301 available_buses = end - busnr; in pci_hp_add_bridge()
3306 if (!dev->subordinate) in pci_hp_add_bridge()
3307 return -1; in pci_hp_add_bridge()