30 #define ASPM_STATE_L0S_DW	(2)	/* Downstream direction L0s state */
51 	struct pci_dev *downstream;	/* Downstream component, function 0 */  member
71 	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
73 	 * Endpoint acceptable latencies. A pcie downstream port only
243 	/* Check downstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
271 	/* Configure downstream component, all functions */  in pcie_aspm_configure_common_clock()
399 		/* Check downstream direction L0s latency */  in pcie_aspm_check_latency()
455 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in aspm_calc_l1ss_info()
488 	 * downstream devices report (via LTR) that they can tolerate at  in aspm_calc_l1ss_info()
545 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_aspm_cap_init()
572 	 * Re-read upstream/downstream components' register state after  in pcie_aspm_cap_init()
687 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_l1ss()
746 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_link()
765 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
781 	 * upstream component first and then downstream, and vice  in pcie_config_aspm_link()
853 	link->downstream = pci_function_0(pdev->subordinate);  in alloc_pcie_link_state()
858 	 * the root ports entirely, in which case a downstream port on  in alloc_pcie_link_state()
895  * @pdev: the root port or switch downstream port
911 	 * downstream port.  in pcie_aspm_init_link_state()
1023 /* @pdev: the root port or switch downstream port */