3  * PCIe host controller driver for NWL PCIe Bridge
4  * Based on pcie-xilinx.c, pci-tegra.c
160 	phys_addr_t phys_pcie_reg_base;	/* Physical PCIe Controller Base */
174 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)  in nwl_bridge_readl()  argument
176 	return readl(pcie->breg_base + off);  in nwl_bridge_readl()
179 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)  in nwl_bridge_writel()  argument
181 	writel(val, pcie->breg_base + off);  in nwl_bridge_writel()
184 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)  in nwl_pcie_link_up()  argument
186 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)  in nwl_pcie_link_up()
191 static bool nwl_phy_link_up(struct nwl_pcie *pcie)  in nwl_phy_link_up()  argument
193 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)  in nwl_phy_link_up()
198 static int nwl_wait_for_link(struct nwl_pcie *pcie)  in nwl_wait_for_link()  argument
200 	struct device *dev = pcie->dev;  in nwl_wait_for_link()
205 		if (nwl_phy_link_up(pcie))  in nwl_wait_for_link()
216 	struct nwl_pcie *pcie = bus->sysdata;  in nwl_pcie_valid_device()  local
220 		if (!nwl_pcie_link_up(pcie))  in nwl_pcie_valid_device()
242 	struct nwl_pcie *pcie = bus->sysdata;  in nwl_pcie_map_bus()  local
251 	return pcie->ecam_base + relbus + where;  in nwl_pcie_map_bus()
254 /* PCIe operations */
263 	struct nwl_pcie *pcie = data;  in nwl_pcie_misc_handler()  local
264 	struct device *dev = pcie->dev;  in nwl_pcie_misc_handler()
268 	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_misc_handler()
313 	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);  in nwl_pcie_misc_handler()
321 	struct nwl_pcie *pcie;  in nwl_pcie_leg_handler()  local
327 	pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_leg_handler()
329 	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_leg_handler()
332 			virq = irq_find_mapping(pcie->legacy_irq_domain, bit);  in nwl_pcie_leg_handler()
341 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)  in nwl_pcie_handle_msi_irq()  argument
348 	msi = &pcie->msi;  in nwl_pcie_handle_msi_irq()
350 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {  in nwl_pcie_handle_msi_irq()
352 			nwl_bridge_writel(pcie, 1 << bit, status_reg);  in nwl_pcie_handle_msi_irq()
363 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_msi_handler_high()  local
366 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);  in nwl_pcie_msi_handler_high()
373 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_msi_handler_low()  local
376 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);  in nwl_pcie_msi_handler_low()
383 	struct nwl_pcie *pcie;  in nwl_mask_leg_irq()  local
388 	pcie = irq_desc_get_chip_data(desc);  in nwl_mask_leg_irq()
390 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);  in nwl_mask_leg_irq()
391 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_mask_leg_irq()
392 	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);  in nwl_mask_leg_irq()
393 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);  in nwl_mask_leg_irq()
399 	struct nwl_pcie *pcie;  in nwl_unmask_leg_irq()  local
404 	pcie = irq_desc_get_chip_data(desc);  in nwl_unmask_leg_irq()
406 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);  in nwl_unmask_leg_irq()
407 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_unmask_leg_irq()
408 	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);  in nwl_unmask_leg_irq()
409 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);  in nwl_unmask_leg_irq()
453 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_compose_msi_msg()  local
454 	phys_addr_t msi_addr = pcie->phys_pcie_reg_base;  in nwl_compose_msi_msg()
476 	struct nwl_pcie *pcie = domain->host_data;  in nwl_irq_domain_alloc()  local
477 	struct nwl_msi *msi = &pcie->msi;  in nwl_irq_domain_alloc()
502 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_irq_domain_free()  local
503 	struct nwl_msi *msi = &pcie->msi;  in nwl_irq_domain_free()
516 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)  in nwl_pcie_init_msi_irq_domain()  argument
519 	struct device *dev = pcie->dev;  in nwl_pcie_init_msi_irq_domain()
521 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_init_msi_irq_domain()
524 						&dev_msi_domain_ops, pcie);  in nwl_pcie_init_msi_irq_domain()
541 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)  in nwl_pcie_init_irq_domain()  argument
543 	struct device *dev = pcie->dev;  in nwl_pcie_init_irq_domain()
553 	pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,  in nwl_pcie_init_irq_domain()
556 							pcie);  in nwl_pcie_init_irq_domain()
558 	if (!pcie->legacy_irq_domain) {  in nwl_pcie_init_irq_domain()
563 	raw_spin_lock_init(&pcie->leg_mask_lock);  in nwl_pcie_init_irq_domain()
564 	nwl_pcie_init_msi_irq_domain(pcie);  in nwl_pcie_init_irq_domain()
568 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)  in nwl_pcie_enable_msi()  argument
570 	struct device *dev = pcie->dev;  in nwl_pcie_enable_msi()
572 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_enable_msi()
591 					 nwl_pcie_msi_handler_high, pcie);  in nwl_pcie_enable_msi()
601 					 nwl_pcie_msi_handler_low, pcie);  in nwl_pcie_enable_msi()
604 	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;  in nwl_pcie_enable_msi()
612 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
616 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
620 	base = pcie->phys_pcie_reg_base;  in nwl_pcie_enable_msi()
621 	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);  in nwl_pcie_enable_msi()
622 	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);  in nwl_pcie_enable_msi()
628 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
630 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &  in nwl_pcie_enable_msi()
633 	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
639 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
641 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &  in nwl_pcie_enable_msi()
644 	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
653 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)  in nwl_pcie_bridge_init()  argument
655 	struct device *dev = pcie->dev;  in nwl_pcie_bridge_init()
660 	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;  in nwl_pcie_bridge_init()
667 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
669 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
673 	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,  in nwl_pcie_bridge_init()
677 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |  in nwl_pcie_bridge_init()
681 	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);  in nwl_pcie_bridge_init()
684 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,  in nwl_pcie_bridge_init()
687 	err = nwl_wait_for_link(pcie);  in nwl_pcie_bridge_init()
691 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;  in nwl_pcie_bridge_init()
698 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
701 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
702 			  (pcie->ecam_value << E_ECAM_SIZE_SHIFT),  in nwl_pcie_bridge_init()
705 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
707 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
711 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);  in nwl_pcie_bridge_init()
712 	pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;  in nwl_pcie_bridge_init()
716 	ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);  in nwl_pcie_bridge_init()
717 	writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));  in nwl_pcie_bridge_init()
719 	if (nwl_pcie_link_up(pcie))  in nwl_pcie_bridge_init()
725 	pcie->irq_misc = platform_get_irq_byname(pdev, "misc");  in nwl_pcie_bridge_init()
726 	if (pcie->irq_misc < 0)  in nwl_pcie_bridge_init()
729 	err = devm_request_irq(dev, pcie->irq_misc,  in nwl_pcie_bridge_init()
731 			       "nwl_pcie:misc", pcie);  in nwl_pcie_bridge_init()
734 			pcie->irq_misc);  in nwl_pcie_bridge_init()
739 	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
742 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_bridge_init()
746 	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
750 	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
753 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_bridge_init()
757 	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
760 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |  in nwl_pcie_bridge_init()
766 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,  in nwl_pcie_parse_dt()  argument
769 	struct device *dev = pcie->dev;  in nwl_pcie_parse_dt()
773 	pcie->breg_base = devm_ioremap_resource(dev, res);  in nwl_pcie_parse_dt()
774 	if (IS_ERR(pcie->breg_base))  in nwl_pcie_parse_dt()
775 		return PTR_ERR(pcie->breg_base);  in nwl_pcie_parse_dt()
776 	pcie->phys_breg_base = res->start;  in nwl_pcie_parse_dt()
779 	pcie->pcireg_base = devm_ioremap_resource(dev, res);  in nwl_pcie_parse_dt()
780 	if (IS_ERR(pcie->pcireg_base))  in nwl_pcie_parse_dt()
781 		return PTR_ERR(pcie->pcireg_base);  in nwl_pcie_parse_dt()
782 	pcie->phys_pcie_reg_base = res->start;  in nwl_pcie_parse_dt()
785 	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);  in nwl_pcie_parse_dt()
786 	if (IS_ERR(pcie->ecam_base))  in nwl_pcie_parse_dt()
787 		return PTR_ERR(pcie->ecam_base);  in nwl_pcie_parse_dt()
788 	pcie->phys_ecam_base = res->start;  in nwl_pcie_parse_dt()
791 	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");  in nwl_pcie_parse_dt()
792 	if (pcie->irq_intx < 0)  in nwl_pcie_parse_dt()
793 		return pcie->irq_intx;  in nwl_pcie_parse_dt()
795 	irq_set_chained_handler_and_data(pcie->irq_intx,  in nwl_pcie_parse_dt()
796 					 nwl_pcie_leg_handler, pcie);  in nwl_pcie_parse_dt()
802 	{ .compatible = "xlnx,nwl-pcie-2.11", },
809 	struct nwl_pcie *pcie;  in nwl_pcie_probe()  local
813 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in nwl_pcie_probe()
817 	pcie = pci_host_bridge_priv(bridge);  in nwl_pcie_probe()
819 	pcie->dev = dev;  in nwl_pcie_probe()
820 	pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;  in nwl_pcie_probe()
822 	err = nwl_pcie_parse_dt(pcie, pdev);  in nwl_pcie_probe()
828 	err = nwl_pcie_bridge_init(pcie);  in nwl_pcie_probe()
834 	err = nwl_pcie_init_irq_domain(pcie);  in nwl_pcie_probe()
840 	bridge->sysdata = pcie;  in nwl_pcie_probe()
844 		err = nwl_pcie_enable_msi(pcie);  in nwl_pcie_probe()
856 		.name = "nwl-pcie",