30 #define RC_PCIE_RST_OUTPUT_SHIFT	0
32 #define PAXC_RESET_MASK			0x7f
34 #define GIC_V3_CFG_SHIFT		0
37 #define MSI_ENABLE_CFG_SHIFT		0
40 #define CFG_IND_ADDR_MASK		0x00001ffc
43 #define CFG_ADDR_BUS_NUM_MASK		0x0ff00000
45 #define CFG_ADDR_DEV_NUM_MASK		0x000f8000
47 #define CFG_ADDR_FUNC_NUM_MASK		0x00007000
49 #define CFG_ADDR_REG_NUM_MASK		0x00000ffc
50 #define CFG_ADDR_CFG_TYPE_SHIFT		0
51 #define CFG_ADDR_CFG_TYPE_MASK		0x00000003
53 #define SYS_RC_INTX_MASK		0xf
60 #define APB_ERR_EN_SHIFT		0
63 #define CFG_RD_SUCCESS			0
67 #define CFG_RETRY_STATUS		0xffff0001
79 #define OARR_VALID_SHIFT		0
89 #define IMAP_VALID_SHIFT		0
92 #define IPROC_PCI_PM_CAP		0x48
93 #define IPROC_PCI_PM_CAP_MASK		0xffff
94 #define IPROC_PCI_EXP_CAP		0xac
96 #define IPROC_PCIE_REG_INVALID		0xffff
150 	IPROC_PCIE_IB_MAP_MEM = 0,
191 		.imap_addr_offset = 0x40,
192 		.imap_window_offset = 0x4,
206 		.imap_addr_offset = 0x4,
207 		.imap_window_offset = 0x8,
216 		.imap_addr_offset = 0x4,
217 		.imap_window_offset = 0x8,
226 		.imap_addr_offset = 0x4,
227 		.imap_window_offset = 0x8,
236 	IPROC_PCIE_CLK_CTRL = 0,
311 	[IPROC_PCIE_CLK_CTRL]		= 0x000,
312 	[IPROC_PCIE_CFG_IND_ADDR]	= 0x120,
313 	[IPROC_PCIE_CFG_IND_DATA]	= 0x124,
314 	[IPROC_PCIE_CFG_ADDR]		= 0x1f8,
315 	[IPROC_PCIE_CFG_DATA]		= 0x1fc,
316 	[IPROC_PCIE_INTX_EN]		= 0x330,
317 	[IPROC_PCIE_LINK_STATUS]	= 0xf0c,
322 	[IPROC_PCIE_CLK_CTRL]		= 0x000,
323 	[IPROC_PCIE_CFG_IND_ADDR]	= 0x120,
324 	[IPROC_PCIE_CFG_IND_DATA]	= 0x124,
325 	[IPROC_PCIE_CFG_ADDR]		= 0x1f8,
326 	[IPROC_PCIE_CFG_DATA]		= 0x1fc,
327 	[IPROC_PCIE_INTX_EN]		= 0x330,
328 	[IPROC_PCIE_OARR0]		= 0xd20,
329 	[IPROC_PCIE_OMAP0]		= 0xd40,
330 	[IPROC_PCIE_OARR1]		= 0xd28,
331 	[IPROC_PCIE_OMAP1]		= 0xd48,
332 	[IPROC_PCIE_LINK_STATUS]	= 0xf0c,
333 	[IPROC_PCIE_APB_ERR_EN]		= 0xf40,
338 	[IPROC_PCIE_CLK_CTRL]		= 0x000,
339 	[IPROC_PCIE_CFG_IND_ADDR]	= 0x120,
340 	[IPROC_PCIE_CFG_IND_DATA]	= 0x124,
341 	[IPROC_PCIE_CFG_ADDR]		= 0x1f8,
342 	[IPROC_PCIE_CFG_DATA]		= 0x1fc,
343 	[IPROC_PCIE_INTX_EN]		= 0x330,
344 	[IPROC_PCIE_OARR0]		= 0xd20,
345 	[IPROC_PCIE_OMAP0]		= 0xd40,
346 	[IPROC_PCIE_OARR1]		= 0xd28,
347 	[IPROC_PCIE_OMAP1]		= 0xd48,
348 	[IPROC_PCIE_OARR2]		= 0xd60,
349 	[IPROC_PCIE_OMAP2]		= 0xd68,
350 	[IPROC_PCIE_OARR3]		= 0xdf0,
351 	[IPROC_PCIE_OMAP3]		= 0xdf8,
352 	[IPROC_PCIE_IARR0]		= 0xd00,
353 	[IPROC_PCIE_IMAP0]		= 0xc00,
354 	[IPROC_PCIE_IARR2]		= 0xd10,
355 	[IPROC_PCIE_IMAP2]		= 0xcc0,
356 	[IPROC_PCIE_IARR3]		= 0xe00,
357 	[IPROC_PCIE_IMAP3]		= 0xe08,
358 	[IPROC_PCIE_IARR4]		= 0xe68,
359 	[IPROC_PCIE_IMAP4]		= 0xe70,
360 	[IPROC_PCIE_CFG_RD_STATUS]	= 0xee0,
361 	[IPROC_PCIE_LINK_STATUS]	= 0xf0c,
362 	[IPROC_PCIE_APB_ERR_EN]		= 0xf40,
367 	[IPROC_PCIE_CLK_CTRL]		= 0x000,
368 	[IPROC_PCIE_CFG_IND_ADDR]	= 0x1f0,
369 	[IPROC_PCIE_CFG_IND_DATA]	= 0x1f4,
370 	[IPROC_PCIE_CFG_ADDR]		= 0x1f8,
371 	[IPROC_PCIE_CFG_DATA]		= 0x1fc,
376 	[IPROC_PCIE_MSI_GIC_MODE]	= 0x050,
377 	[IPROC_PCIE_MSI_BASE_ADDR]	= 0x074,
378 	[IPROC_PCIE_MSI_WINDOW_SIZE]	= 0x078,
379 	[IPROC_PCIE_MSI_ADDR_LO]	= 0x07c,
380 	[IPROC_PCIE_MSI_ADDR_HI]	= 0x080,
381 	[IPROC_PCIE_MSI_EN_CFG]		= 0x09c,
382 	[IPROC_PCIE_CFG_IND_ADDR]	= 0x1f0,
383 	[IPROC_PCIE_CFG_IND_DATA]	= 0x1f4,
384 	[IPROC_PCIE_CFG_ADDR]		= 0x1f8,
385 	[IPROC_PCIE_CFG_DATA]		= 0x1fc,
393 	0x16cd,
394 	0x16f0,
395 	0xd802,
396 	0xd804
422 		return 0;  in iproc_pcie_read_reg()
507 	 * eventually return the wrong data (0xffffffff).  in iproc_pcie_cfg_retry()
525 		data = 0xffffffff;  in iproc_pcie_cfg_retry()
534 	switch (where & ~0x3) {  in iproc_pcie_fix_cap()
542 		for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++)  in iproc_pcie_fix_cap()
585 	if (busno == 0) {  in iproc_pcie_config_read()
612 	 * ID of 0x168e (PCI_DEVICE_ID_NX2_57810), we try to catch those access  in iproc_pcie_config_read()
615 #define DEVICE_ID_MASK     0xffff0000  in iproc_pcie_config_read()
639 	if (busno == 0) {  in iproc_pcie_map_cfg_bus()
640 		if (slot > 0 || fn > 0)  in iproc_pcie_map_cfg_bus()
669 	addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);  in iproc_pci_raw_config_read32()
671 		*val = ~0;  in iproc_pci_raw_config_read32()
690 	addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);  in iproc_pci_raw_config_write32()
699 	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));  in iproc_pci_raw_config_write32()
701 	tmp |= val << ((where & 0x3) * 8);  in iproc_pci_raw_config_write32()
772 	return 0;  in iproc_pcie_shutdown()
787 		return 0;  in iproc_pcie_check_link()
796 	iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);  in iproc_pcie_check_link()
797 	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {  in iproc_pcie_check_link()
802 	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */  in iproc_pcie_check_link()
803 #define PCI_BRIDGE_CTRL_REG_OFFSET	0x43c  in iproc_pcie_check_link()
804 #define PCI_CLASS_BRIDGE_MASK		0xffff00  in iproc_pcie_check_link()
806 	iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,  in iproc_pcie_check_link()
810 	iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,  in iproc_pcie_check_link()
814 	iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,  in iproc_pcie_check_link()
821 #define PCI_TARGET_LINK_SPEED_MASK	0xf  in iproc_pcie_check_link()
822 #define PCI_TARGET_LINK_SPEED_GEN2	0x2  in iproc_pcie_check_link()
823 #define PCI_TARGET_LINK_SPEED_GEN1	0x1  in iproc_pcie_check_link()
824 		iproc_pci_raw_config_read32(pcie, 0,  in iproc_pcie_check_link()
831 			iproc_pci_raw_config_write32(pcie, 0,  in iproc_pcie_check_link()
836 			iproc_pci_raw_config_read32(pcie, 0,  in iproc_pcie_check_link()
846 	return link_is_active ? 0 : -ENODEV;  in iproc_pcie_check_link()
894 	dev_dbg(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",  in iproc_pcie_ob_write()
896 	dev_dbg(dev, "oarr lo 0x%x oarr hi 0x%x\n",  in iproc_pcie_ob_write()
899 	dev_dbg(dev, "omap lo 0x%x omap hi 0x%x\n",  in iproc_pcie_ob_write()
903 	return 0;  in iproc_pcie_ob_write()
937 	for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {  in iproc_pcie_setup_ob()
953 		for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;  in iproc_pcie_setup_ob()
965 				if (size_idx > 0 || window_idx > 0)  in iproc_pcie_setup_ob()
996 			if (size == 0)  in iproc_pcie_setup_ob()
997 				return 0;  in iproc_pcie_setup_ob()
1047 	return 0;  in iproc_pcie_map_ranges()
1085 	dev_dbg(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",  in iproc_pcie_ib_write()
1096 	dev_dbg(dev, "iarr lo 0x%x iarr hi 0x%x\n",  in iproc_pcie_ib_write()
1105 	for (window_idx = 0; window_idx < nr_windows; window_idx++) {  in iproc_pcie_ib_write()
1112 		dev_dbg(dev, "imap window [%d] lo 0x%x hi 0x%x\n",  in iproc_pcie_ib_write()
1121 	return 0;  in iproc_pcie_ib_write()
1137 	for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {  in iproc_pcie_setup_ib()
1150 		for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {  in iproc_pcie_setup_ib()
1172 				return 0;  in iproc_pcie_setup_ib()
1190 	int ret = 0;  in iproc_pcie_map_dma_ranges()
1213 		for (idx = ob->nr_windows - 1; idx >= 0; idx--) {  in iproc_pcie_invalidate_mapping()
1215 					     MAP_REG(IPROC_PCIE_OARR0, idx), 0);  in iproc_pcie_invalidate_mapping()
1221 		for (idx = 0; idx < ib->nr_regions; idx++) {  in iproc_pcie_invalidate_mapping()
1223 					     MAP_REG(IPROC_PCIE_IARR0, idx), 0);  in iproc_pcie_invalidate_mapping()
1246 	ret = of_address_to_resource(msi_node, 0, &res);  in iproce_pcie_get_msi()
1247 	if (ret < 0) {  in iproce_pcie_get_msi()
1253 	return 0;  in iproce_pcie_get_msi()
1261 	memset(&entry, 0, sizeof(entry));  in iproc_pcie_paxb_v2_msi_steer()
1290 	 * bits [30:0] of the MSI base address register.  In fact, in all iProc  in iproc_pcie_paxc_v2_msi_steer()
1298 	iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0);  in iproc_pcie_paxc_v2_msi_steer()
1329 	if (ret < 0) {  in iproc_pcie_msi_steer()
1347 	return 0;  in iproc_pcie_msi_steer()
1360 	msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);  in iproc_pcie_msi_enable()
1460 	pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?  in iproc_pcie_rev_init()
1461 		IPROC_PCIE_REG_INVALID : regs[0];  in iproc_pcie_rev_init()
1466 	return 0;  in iproc_pcie_rev_init()
1531 	if (ret < 0) {  in iproc_pcie_setup()
1536 	return 0;  in iproc_pcie_setup()
1558 	return 0;  in iproc_pcie_remove()
1571 		iproc_pcie_paxc_v2_msi_steer(pcie, 0, false);  in quirk_paxc_disable_msi_parsing()
1573 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0,
1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802,
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,
1591 	 * MPSS is not being set properly (as it is currently 0).  This is  in quirk_paxc_bridge()
1598 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
1599 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
1600 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
1601 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
1602 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);