Lines Matching +full:0 +full:xfffffe00
19 #define PEM_CFG_WR 0x28
20 #define PEM_CFG_RD 0x30
34 if (devfn != 0 || where >= 2048) { in thunder_pem_bridge_read()
35 *val = ~0; in thunder_pem_bridge_read()
54 case 0x40: in thunder_pem_bridge_read()
55 read_val &= 0xffff00ff; in thunder_pem_bridge_read()
56 read_val |= 0x00007000; /* Skip MSI CAP */ in thunder_pem_bridge_read()
58 case 0x70: /* Express Cap */ in thunder_pem_bridge_read()
61 * reads as 0, else leave it alone. in thunder_pem_bridge_read()
63 if (!(read_val & (0x1f << 25))) in thunder_pem_bridge_read()
66 case 0xb0: /* MSI-X Cap */ in thunder_pem_bridge_read()
68 read_val &= 0xc00000ff; in thunder_pem_bridge_read()
70 * If Express Cap(0x70) raw PME vector reads as 0 we are on in thunder_pem_bridge_read()
74 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD); in thunder_pem_bridge_read()
77 if (!(tmp_val & (0x1f << 25))) in thunder_pem_bridge_read()
78 read_val |= 0x0003bc00; in thunder_pem_bridge_read()
80 read_val |= 0x0001bc00; in thunder_pem_bridge_read()
82 case 0xb4: in thunder_pem_bridge_read()
83 /* Table offset=0, BIR=0 */ in thunder_pem_bridge_read()
84 read_val = 0x00000000; in thunder_pem_bridge_read()
86 case 0xb8: in thunder_pem_bridge_read()
87 /* BPA offset=0xf0000, BIR=0 */ in thunder_pem_bridge_read()
88 read_val = 0x000f0000; in thunder_pem_bridge_read()
90 case 0xbc: in thunder_pem_bridge_read()
92 read_val = 0x00010014; in thunder_pem_bridge_read()
94 case 0xc0: in thunder_pem_bridge_read()
96 read_val = 0x00000000; in thunder_pem_bridge_read()
98 case 0xc4: in thunder_pem_bridge_read()
99 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */ in thunder_pem_bridge_read()
100 read_val = 0x80ff0003; in thunder_pem_bridge_read()
102 case 0xc8: in thunder_pem_bridge_read()
103 read_val = pem_pci->ea_entry[0]; in thunder_pem_bridge_read()
105 case 0xcc: in thunder_pem_bridge_read()
108 case 0xd0: in thunder_pem_bridge_read()
117 read_val &= 0xff; in thunder_pem_bridge_read()
120 read_val &= 0xffff; in thunder_pem_bridge_read()
155 u32 w1c_bits = 0; in thunder_pem_bridge_w1c_bits()
158 case 0x04: /* Command/Status */ in thunder_pem_bridge_w1c_bits()
159 case 0x1c: /* Base and I/O Limit/Secondary Status */ in thunder_pem_bridge_w1c_bits()
160 w1c_bits = 0xff000000; in thunder_pem_bridge_w1c_bits()
162 case 0x44: /* Power Management Control and Status */ in thunder_pem_bridge_w1c_bits()
163 w1c_bits = 0xfffffe00; in thunder_pem_bridge_w1c_bits()
165 case 0x78: /* Device Control/Device Status */ in thunder_pem_bridge_w1c_bits()
166 case 0x80: /* Link Control/Link Status */ in thunder_pem_bridge_w1c_bits()
167 case 0x88: /* Slot Control/Slot Status */ in thunder_pem_bridge_w1c_bits()
168 case 0x90: /* Root Status */ in thunder_pem_bridge_w1c_bits()
169 case 0xa0: /* Link Control 2 Registers/Link Status 2 */ in thunder_pem_bridge_w1c_bits()
170 w1c_bits = 0xffff0000; in thunder_pem_bridge_w1c_bits()
172 case 0x104: /* Uncorrectable Error Status */ in thunder_pem_bridge_w1c_bits()
173 case 0x110: /* Correctable Error Status */ in thunder_pem_bridge_w1c_bits()
174 case 0x130: /* Error Status */ in thunder_pem_bridge_w1c_bits()
175 case 0x160: /* Link Control 4 */ in thunder_pem_bridge_w1c_bits()
176 w1c_bits = 0xffffffff; in thunder_pem_bridge_w1c_bits()
190 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */ in thunder_pem_bridge_w1_bits()
192 w1_bits = 0x0101; in thunder_pem_bridge_w1_bits()
194 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */ in thunder_pem_bridge_w1_bits()
196 w1_bits = 0x00010001; in thunder_pem_bridge_w1_bits()
199 w1_bits = 0; in thunder_pem_bridge_w1_bits()
212 u32 mask = 0; in thunder_pem_bridge_write()
215 if (devfn != 0 || where >= 2048) in thunder_pem_bridge_write()
229 mask = ~(0xff << (8 * (where & 3))); in thunder_pem_bridge_write()
231 val = (val & 0xff) << (8 * (where & 3)); in thunder_pem_bridge_write()
238 mask = ~(0xffff << (8 * (where & 3))); in thunder_pem_bridge_write()
240 val = (val & 0xffff) << (8 * (where & 3)); in thunder_pem_bridge_write()
307 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000); in thunder_pem_init()
317 bar4_start = res_pem->start + 0xf00000; in thunder_pem_init()
318 pem_pci->ea_entry[0] = (u32)bar4_start | 2; in thunder_pem_init()
323 return 0; in thunder_pem_init()
328 #define PEM_RES_BASE 0x87e0c0000000UL
362 node = 0; in thunder_pem_legacy_fw()