Lines Matching +full:pcie +full:- +full:ep
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
23 #include "pcie-designware.h"
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
34 struct regmap *regmap; /* DT axis,syscon-pcie */
47 /* ARTPEC-6 specific registers */
61 /* ARTPEC-7 specific fields */
66 /* ARTPEC-7 specific fields */
88 regmap_read(artpec6_pcie->regmap, offset, &val); in artpec6_pcie_readl()
94 regmap_write(artpec6_pcie->regmap, offset, val); in artpec6_pcie_writel()
100 struct pcie_port *pp = &pci->pp; in artpec6_pcie_cpu_addr_fixup()
101 struct dw_pcie_ep *ep = &pci->ep; in artpec6_pcie_cpu_addr_fixup() local
103 switch (artpec6_pcie->mode) { in artpec6_pcie_cpu_addr_fixup()
105 return pci_addr - pp->cfg0_base; in artpec6_pcie_cpu_addr_fixup()
107 return pci_addr - ep->phys_base; in artpec6_pcie_cpu_addr_fixup()
109 dev_err(pci->dev, "UNKNOWN device type\n"); in artpec6_pcie_cpu_addr_fixup()
144 struct dw_pcie *pci = artpec6_pcie->pci; in artpec6_pcie_wait_for_phy_a6()
145 struct device *dev = pci->dev; in artpec6_pcie_wait_for_phy_a6()
153 retries--; in artpec6_pcie_wait_for_phy_a6()
157 dev_err(dev, "PCIe clock manager did not leave idle state\n"); in artpec6_pcie_wait_for_phy_a6()
162 val = readl(artpec6_pcie->phy_base + PHY_STATUS); in artpec6_pcie_wait_for_phy_a6()
163 retries--; in artpec6_pcie_wait_for_phy_a6()
171 struct dw_pcie *pci = artpec6_pcie->pci; in artpec6_pcie_wait_for_phy_a7()
172 struct device *dev = pci->dev; in artpec6_pcie_wait_for_phy_a7()
181 retries--; in artpec6_pcie_wait_for_phy_a7()
185 dev_err(dev, "PCIe clock manager did not leave idle state\n"); in artpec6_pcie_wait_for_phy_a7()
190 phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT); in artpec6_pcie_wait_for_phy_a7()
191 phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT); in artpec6_pcie_wait_for_phy_a7()
192 retries--; in artpec6_pcie_wait_for_phy_a7()
201 switch (artpec6_pcie->variant) { in artpec6_pcie_wait_for_phy()
243 struct dw_pcie *pci = artpec6_pcie->pci; in artpec6_pcie_init_phy_a7()
250 dev_dbg(pci->dev, "Using reference clock: %s\n", in artpec6_pcie_init_phy_a7()
275 switch (artpec6_pcie->variant) { in artpec6_pcie_init_phy()
290 switch (artpec6_pcie->variant) { in artpec6_pcie_assert_core_reset()
306 switch (artpec6_pcie->variant) { in artpec6_pcie_deassert_core_reset()
323 if (artpec6_pcie->variant == ARTPEC7) { in artpec6_pcie_host_init()
324 pci->n_fts[0] = 180; in artpec6_pcie_host_init()
325 pci->n_fts[1] = 180; in artpec6_pcie_host_init()
346 struct dw_pcie *pci = artpec6_pcie->pci; in artpec6_add_pcie_port()
347 struct pcie_port *pp = &pci->pp; in artpec6_add_pcie_port()
348 struct device *dev = pci->dev; in artpec6_add_pcie_port()
352 pp->msi_irq = platform_get_irq_byname(pdev, "msi"); in artpec6_add_pcie_port()
353 if (pp->msi_irq < 0) in artpec6_add_pcie_port()
354 return pp->msi_irq; in artpec6_add_pcie_port()
357 pp->ops = &artpec6_pcie_host_ops; in artpec6_add_pcie_port()
368 static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep) in artpec6_pcie_ep_init() argument
370 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in artpec6_pcie_ep_init()
383 static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, in artpec6_pcie_raise_irq() argument
386 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in artpec6_pcie_raise_irq()
390 dev_err(pci->dev, "EP cannot trigger legacy IRQs\n"); in artpec6_pcie_raise_irq()
391 return -EINVAL; in artpec6_pcie_raise_irq()
393 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); in artpec6_pcie_raise_irq()
395 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in artpec6_pcie_raise_irq()
410 struct dw_pcie_ep *ep; in artpec6_add_pcie_ep() local
412 struct device *dev = &pdev->dev; in artpec6_add_pcie_ep()
413 struct dw_pcie *pci = artpec6_pcie->pci; in artpec6_add_pcie_ep()
415 ep = &pci->ep; in artpec6_add_pcie_ep()
416 ep->ops = &pcie_ep_ops; in artpec6_add_pcie_ep()
418 pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); in artpec6_add_pcie_ep()
419 if (IS_ERR(pci->dbi_base2)) in artpec6_add_pcie_ep()
420 return PTR_ERR(pci->dbi_base2); in artpec6_add_pcie_ep()
424 return -EINVAL; in artpec6_add_pcie_ep()
426 ep->phys_base = res->start; in artpec6_add_pcie_ep()
427 ep->addr_size = resource_size(res); in artpec6_add_pcie_ep()
429 ret = dw_pcie_ep_init(ep); in artpec6_add_pcie_ep()
440 struct device *dev = &pdev->dev; in artpec6_pcie_probe()
451 return -EINVAL; in artpec6_pcie_probe()
453 data = (struct artpec_pcie_of_data *)match->data; in artpec6_pcie_probe()
454 variant = (enum artpec_pcie_variants)data->variant; in artpec6_pcie_probe()
455 mode = (enum dw_pcie_device_mode)data->mode; in artpec6_pcie_probe()
459 return -ENOMEM; in artpec6_pcie_probe()
463 return -ENOMEM; in artpec6_pcie_probe()
465 pci->dev = dev; in artpec6_pcie_probe()
466 pci->ops = &dw_pcie_ops; in artpec6_pcie_probe()
468 artpec6_pcie->pci = pci; in artpec6_pcie_probe()
469 artpec6_pcie->variant = variant; in artpec6_pcie_probe()
470 artpec6_pcie->mode = mode; in artpec6_pcie_probe()
472 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); in artpec6_pcie_probe()
473 if (IS_ERR(pci->dbi_base)) in artpec6_pcie_probe()
474 return PTR_ERR(pci->dbi_base); in artpec6_pcie_probe()
476 artpec6_pcie->phy_base = in artpec6_pcie_probe()
478 if (IS_ERR(artpec6_pcie->phy_base)) in artpec6_pcie_probe()
479 return PTR_ERR(artpec6_pcie->phy_base); in artpec6_pcie_probe()
481 artpec6_pcie->regmap = in artpec6_pcie_probe()
482 syscon_regmap_lookup_by_phandle(dev->of_node, in artpec6_pcie_probe()
483 "axis,syscon-pcie"); in artpec6_pcie_probe()
484 if (IS_ERR(artpec6_pcie->regmap)) in artpec6_pcie_probe()
485 return PTR_ERR(artpec6_pcie->regmap); in artpec6_pcie_probe()
489 switch (artpec6_pcie->mode) { in artpec6_pcie_probe()
492 return -ENODEV; in artpec6_pcie_probe()
502 return -ENODEV; in artpec6_pcie_probe()
513 dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode); in artpec6_pcie_probe()
541 .compatible = "axis,artpec6-pcie",
545 .compatible = "axis,artpec6-pcie-ep",
549 .compatible = "axis,artpec7-pcie",
553 .compatible = "axis,artpec7-pcie-ep",
562 .name = "artpec6-pcie",