Lines Matching +full:no +full:- +full:bar +full:- +full:match +full:- +full:nbits
1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
31 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus()
32 unsigned int busn = bus->number; in cdns_pci_map_bus()
44 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 /* Clear AXI link-down status */ in cdns_pci_map_bus()
65 if (busn == bridge->busnr + 1) in cdns_pci_map_bus()
71 return rc->cfg_base + (where & 0xfff); in cdns_pci_map_bus()
83 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_init_root_port()
88 * Set the root complex BAR configuration register: in cdns_pcie_host_init_root_port()
89 * - disable both BAR0 and BAR1. in cdns_pcie_host_init_root_port()
90 * - enable Prefetchable Memory Base and Limit registers in type 1 in cdns_pcie_host_init_root_port()
92 * - enable IO Base and Limit registers in type 1 config in cdns_pcie_host_init_root_port()
105 if (rc->vendor_id != 0xffff) { in cdns_pcie_host_init_root_port()
106 id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | in cdns_pcie_host_init_root_port()
107 CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); in cdns_pcie_host_init_root_port()
111 if (rc->device_id != 0xffff) in cdns_pcie_host_init_root_port()
112 cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); in cdns_pcie_host_init_root_port()
122 enum cdns_pcie_rp_bar bar, in cdns_pcie_host_bar_ib_config() argument
126 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_bar_ib_config()
129 if (!rc->avail_ib_bar[bar]) in cdns_pcie_host_bar_ib_config()
130 return -EBUSY; in cdns_pcie_host_bar_ib_config()
132 rc->avail_ib_bar[bar] = false; in cdns_pcie_host_bar_ib_config()
138 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0); in cdns_pcie_host_bar_ib_config()
139 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1); in cdns_pcie_host_bar_ib_config()
141 if (bar == RP_NO_BAR) in cdns_pcie_host_bar_ib_config()
145 value &= ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | in cdns_pcie_host_bar_ib_config()
146 LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | in cdns_pcie_host_bar_ib_config()
147 LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | in cdns_pcie_host_bar_ib_config()
148 LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | in cdns_pcie_host_bar_ib_config()
149 LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2)); in cdns_pcie_host_bar_ib_config()
152 value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); in cdns_pcie_host_bar_ib_config()
153 value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); in cdns_pcie_host_bar_ib_config()
156 value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); in cdns_pcie_host_bar_ib_config()
157 value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); in cdns_pcie_host_bar_ib_config()
160 value |= LM_RC_BAR_CFG_APERTURE(bar, aperture); in cdns_pcie_host_bar_ib_config()
169 enum cdns_pcie_rp_bar bar, sel_bar; in cdns_pcie_host_find_min_bar() local
172 for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { in cdns_pcie_host_find_min_bar()
173 if (!rc->avail_ib_bar[bar]) in cdns_pcie_host_find_min_bar()
176 if (size <= bar_max_size[bar]) { in cdns_pcie_host_find_min_bar()
178 sel_bar = bar; in cdns_pcie_host_find_min_bar()
182 if (bar_max_size[bar] < bar_max_size[sel_bar]) in cdns_pcie_host_find_min_bar()
183 sel_bar = bar; in cdns_pcie_host_find_min_bar()
193 enum cdns_pcie_rp_bar bar, sel_bar; in cdns_pcie_host_find_max_bar() local
196 for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { in cdns_pcie_host_find_max_bar()
197 if (!rc->avail_ib_bar[bar]) in cdns_pcie_host_find_max_bar()
200 if (size >= bar_max_size[bar]) { in cdns_pcie_host_find_max_bar()
202 sel_bar = bar; in cdns_pcie_host_find_max_bar()
206 if (bar_max_size[bar] > bar_max_size[sel_bar]) in cdns_pcie_host_find_max_bar()
207 sel_bar = bar; in cdns_pcie_host_find_max_bar()
218 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_bar_config()
219 struct device *dev = pcie->dev; in cdns_pcie_host_bar_config()
220 enum cdns_pcie_rp_bar bar; in cdns_pcie_host_bar_config() local
224 cpu_addr = entry->res->start; in cdns_pcie_host_bar_config()
225 pci_addr = entry->res->start - entry->offset; in cdns_pcie_host_bar_config()
226 flags = entry->res->flags; in cdns_pcie_host_bar_config()
227 size = resource_size(entry->res); in cdns_pcie_host_bar_config()
229 if (entry->offset) { in cdns_pcie_host_bar_config()
232 return -EINVAL; in cdns_pcie_host_bar_config()
237 * Try to find a minimum BAR whose size is greater than in cdns_pcie_host_bar_config()
241 * If a minimum BAR is found, IB ATU will be configured and in cdns_pcie_host_bar_config()
244 bar = cdns_pcie_host_find_min_bar(rc, size); in cdns_pcie_host_bar_config()
245 if (bar != RP_BAR_UNDEFINED) { in cdns_pcie_host_bar_config()
246 ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, in cdns_pcie_host_bar_config()
249 dev_err(dev, "IB BAR: %d config failed\n", bar); in cdns_pcie_host_bar_config()
255 * resource_entry size cannot be fitted in a single BAR. So we in cdns_pcie_host_bar_config()
256 * find a maximum BAR whose size is less than or equal to the in cdns_pcie_host_bar_config()
259 * BAR. The remaining size would be fitted during the next in cdns_pcie_host_bar_config()
261 * If a maximum BAR is not found, there is no way we can fit in cdns_pcie_host_bar_config()
264 bar = cdns_pcie_host_find_max_bar(rc, size); in cdns_pcie_host_bar_config()
265 if (bar == RP_BAR_UNDEFINED) { in cdns_pcie_host_bar_config()
266 dev_err(dev, "No free BAR to map cpu_addr %llx\n", in cdns_pcie_host_bar_config()
268 return -EINVAL; in cdns_pcie_host_bar_config()
271 winsize = bar_max_size[bar]; in cdns_pcie_host_bar_config()
272 ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize, in cdns_pcie_host_bar_config()
275 dev_err(dev, "IB BAR: %d config failed\n", bar); in cdns_pcie_host_bar_config()
279 size -= winsize; in cdns_pcie_host_bar_config()
293 return resource_size(entry2->res) - resource_size(entry1->res); in cdns_pcie_host_dma_ranges_cmp()
298 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_map_dma_ranges()
299 struct device *dev = pcie->dev; in cdns_pcie_host_map_dma_ranges()
300 struct device_node *np = dev->of_node; in cdns_pcie_host_map_dma_ranges()
308 return -ENOMEM; in cdns_pcie_host_map_dma_ranges()
310 if (list_empty(&bridge->dma_ranges)) { in cdns_pcie_host_map_dma_ranges()
311 of_property_read_u32(np, "cdns,no-bar-match-nbits", in cdns_pcie_host_map_dma_ranges()
316 dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); in cdns_pcie_host_map_dma_ranges()
320 list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); in cdns_pcie_host_map_dma_ranges()
322 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in cdns_pcie_host_map_dma_ranges()
325 dev_err(dev, "Fail to configure IB using dma-ranges\n"); in cdns_pcie_host_map_dma_ranges()
334 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_init_address_translation()
336 struct resource *cfg_res = rc->cfg_res; in cdns_pcie_host_init_address_translation()
338 u64 cpu_addr = cfg_res->start; in cdns_pcie_host_init_address_translation()
342 entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); in cdns_pcie_host_init_address_translation()
344 busnr = entry->res->start; in cdns_pcie_host_init_address_translation()
356 if (pcie->ops->cpu_addr_fixup) in cdns_pcie_host_init_address_translation()
357 cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); in cdns_pcie_host_init_address_translation()
366 resource_list_for_each_entry(entry, &bridge->windows) { in cdns_pcie_host_init_address_translation()
367 struct resource *res = entry->res; in cdns_pcie_host_init_address_translation()
368 u64 pci_addr = res->start - entry->offset; in cdns_pcie_host_init_address_translation()
373 pci_pio_to_address(res->start), in cdns_pcie_host_init_address_translation()
379 res->start, in cdns_pcie_host_init_address_translation()
403 struct device *dev = pcie->dev; in cdns_pcie_host_wait_for_link()
415 return -ETIMEDOUT; in cdns_pcie_host_wait_for_link()
420 struct device *dev = rc->pcie.dev; in cdns_pcie_host_setup()
422 struct device_node *np = dev->of_node; in cdns_pcie_host_setup()
424 enum cdns_pcie_rp_bar bar; in cdns_pcie_host_setup() local
431 return -ENOMEM; in cdns_pcie_host_setup()
433 pcie = &rc->pcie; in cdns_pcie_host_setup()
434 pcie->is_rc = true; in cdns_pcie_host_setup()
436 rc->vendor_id = 0xffff; in cdns_pcie_host_setup()
437 of_property_read_u32(np, "vendor-id", &rc->vendor_id); in cdns_pcie_host_setup()
439 rc->device_id = 0xffff; in cdns_pcie_host_setup()
440 of_property_read_u32(np, "device-id", &rc->device_id); in cdns_pcie_host_setup()
442 pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); in cdns_pcie_host_setup()
443 if (IS_ERR(pcie->reg_base)) { in cdns_pcie_host_setup()
445 return PTR_ERR(pcie->reg_base); in cdns_pcie_host_setup()
449 rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); in cdns_pcie_host_setup()
450 if (IS_ERR(rc->cfg_base)) in cdns_pcie_host_setup()
451 return PTR_ERR(rc->cfg_base); in cdns_pcie_host_setup()
452 rc->cfg_res = res; in cdns_pcie_host_setup()
464 for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) in cdns_pcie_host_setup()
465 rc->avail_ib_bar[bar] = true; in cdns_pcie_host_setup()
471 if (!bridge->ops) in cdns_pcie_host_setup()
472 bridge->ops = &cdns_pcie_host_ops; in cdns_pcie_host_setup()