19 static int gen4_poll_link(struct intel_ntb_dev *ndev);
20 static int gen4_link_is_up(struct intel_ntb_dev *ndev);
49 static int gen4_poll_link(struct intel_ntb_dev *ndev)  in gen4_poll_link()  argument
57 	iowrite16(GEN4_SLOTSTS_DLLSCS, ndev->self_mmio + GEN4_SLOTSTS);  in gen4_poll_link()
58 	ndev->reg->db_iowrite(ndev->db_link_mask,  in gen4_poll_link()
59 			      ndev->self_mmio +  in gen4_poll_link()
60 			      ndev->self_reg->db_clear);  in gen4_poll_link()
62 	reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET);  in gen4_poll_link()
63 	if (reg_val == ndev->lnk_sta)  in gen4_poll_link()
66 	ndev->lnk_sta = reg_val;  in gen4_poll_link()
71 static int gen4_link_is_up(struct intel_ntb_dev *ndev)  in gen4_link_is_up()  argument
73 	return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);  in gen4_link_is_up()
76 static int gen4_init_isr(struct intel_ntb_dev *ndev)  in gen4_init_isr()  argument
88 		iowrite8(i, ndev->self_mmio + GEN4_INTVEC_OFFSET + i);  in gen4_init_isr()
90 	return ndev_init_isr(ndev, GEN4_DB_MSIX_VECTOR_COUNT,  in gen4_init_isr()
96 static int gen4_setup_b2b_mw(struct intel_ntb_dev *ndev,  in gen4_setup_b2b_mw()  argument
104 	pdev = ndev->ntb.pdev;  in gen4_setup_b2b_mw()
105 	mmio = ndev->self_mmio;  in gen4_setup_b2b_mw()
122 	ndev->peer_mmio = ndev->self_mmio;  in gen4_setup_b2b_mw()
127 static int gen4_init_ntb(struct intel_ntb_dev *ndev)  in gen4_init_ntb()  argument
132 	ndev->mw_count = XEON_MW_COUNT;  in gen4_init_ntb()
133 	ndev->spad_count = GEN4_SPAD_COUNT;  in gen4_init_ntb()
134 	ndev->db_count = GEN4_DB_COUNT;  in gen4_init_ntb()
135 	ndev->db_link_mask = GEN4_DB_LINK_BIT;  in gen4_init_ntb()
137 	ndev->self_reg = &gen4_pri_reg;  in gen4_init_ntb()
138 	ndev->xlat_reg = &gen4_sec_xlat;  in gen4_init_ntb()
139 	ndev->peer_reg = &gen4_b2b_reg;  in gen4_init_ntb()
141 	if (ndev->ntb.topo == NTB_TOPO_B2B_USD)  in gen4_init_ntb()
142 		rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_dsd_addr,  in gen4_init_ntb()
145 		rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_usd_addr,  in gen4_init_ntb()
150 	ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;  in gen4_init_ntb()
152 	ndev->reg->db_iowrite(ndev->db_valid_mask,  in gen4_init_ntb()
153 			      ndev->self_mmio +  in gen4_init_ntb()
154 			      ndev->self_reg->db_mask);  in gen4_init_ntb()
159 static enum ntb_topo gen4_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)  in gen4_ppd_topo()  argument
171 int gen4_init_dev(struct intel_ntb_dev *ndev)  in gen4_init_dev()  argument
173 	struct pci_dev *pdev = ndev->ntb.pdev;  in gen4_init_dev()
178 	ndev->reg = &gen4_reg;  in gen4_init_dev()
181 		ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN;  in gen4_init_dev()
183 	ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);  in gen4_init_dev()
184 	ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);  in gen4_init_dev()
186 		ntb_topo_string(ndev->ntb.topo));  in gen4_init_dev()
187 	if (ndev->ntb.topo == NTB_TOPO_NONE)  in gen4_init_dev()
190 	rc = gen4_init_ntb(ndev);  in gen4_init_dev()
195 	lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);  in gen4_init_dev()
197 	iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);  in gen4_init_dev()
199 	return gen4_init_isr(ndev);  in gen4_init_dev()
205 	struct intel_ntb_dev *ndev;  in ndev_ntb4_debugfs_read()  local
212 	ndev = filp->private_data;  in ndev_ntb4_debugfs_read()
213 	mmio = ndev->self_mmio;  in ndev_ntb4_debugfs_read()
228 			 ntb_topo_string(ndev->ntb.topo));  in ndev_ntb4_debugfs_read()
231 			 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);  in ndev_ntb4_debugfs_read()
233 			 "LNK STA (cached) -\t\t%#06x\n", ndev->lnk_sta);  in ndev_ntb4_debugfs_read()
235 	if (!ndev->reg->link_is_up(ndev))  in ndev_ntb4_debugfs_read()
243 				 NTB_LNK_STA_SPEED(ndev->lnk_sta));  in ndev_ntb4_debugfs_read()
246 				 NTB_LNK_STA_WIDTH(ndev->lnk_sta));  in ndev_ntb4_debugfs_read()
250 			 "Memory Window Count -\t%u\n", ndev->mw_count);  in ndev_ntb4_debugfs_read()
252 			 "Scratchpad Count -\t%u\n", ndev->spad_count);  in ndev_ntb4_debugfs_read()
254 			 "Doorbell Count -\t%u\n", ndev->db_count);  in ndev_ntb4_debugfs_read()
256 			 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);  in ndev_ntb4_debugfs_read()
258 			 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);  in ndev_ntb4_debugfs_read()
261 			 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);  in ndev_ntb4_debugfs_read()
263 			 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);  in ndev_ntb4_debugfs_read()
265 			 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);  in ndev_ntb4_debugfs_read()
267 	u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);  in ndev_ntb4_debugfs_read()
296 	if (!pci_read_config_word(ndev->ntb.pdev,  in ndev_ntb4_debugfs_read()
305 	if (!pci_read_config_dword(ndev->ntb.pdev,  in ndev_ntb4_debugfs_read()
310 	if (!pci_read_config_dword(ndev->ntb.pdev,  in ndev_ntb4_debugfs_read()
323 	struct intel_ntb_dev *ndev = ntb_ndev(ntb);  in intel_ntb4_mw_set_trans()  local
334 	if (idx >= ndev->b2b_idx && !ndev->b2b_off)  in intel_ntb4_mw_set_trans()
337 	bar = ndev_mw_to_bar(ndev, idx);  in intel_ntb4_mw_set_trans()
341 	bar_size = pci_resource_len(ndev->ntb.pdev, bar);  in intel_ntb4_mw_set_trans()
343 	if (idx == ndev->b2b_idx)  in intel_ntb4_mw_set_trans()
344 		mw_size = bar_size - ndev->b2b_off;  in intel_ntb4_mw_set_trans()
348 	if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {  in intel_ntb4_mw_set_trans()
361 	mmio = ndev->self_mmio;  in intel_ntb4_mw_set_trans()
362 	xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);  in intel_ntb4_mw_set_trans()
363 	limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);  in intel_ntb4_mw_set_trans()
364 	base = pci_resource_start(ndev->ntb.pdev, bar);  in intel_ntb4_mw_set_trans()
397 	if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {  in intel_ntb4_mw_set_trans()
398 		idx_reg = ndev->xlat_reg->bar2_idx + (idx * 0x2);  in intel_ntb4_mw_set_trans()
417 	struct intel_ntb_dev *ndev;  in intel_ntb4_link_enable()  local
421 	ndev = container_of(ntb, struct intel_ntb_dev, ntb);  in intel_ntb4_link_enable()
436 	iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);  in intel_ntb4_link_enable()
438 	lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);  in intel_ntb4_link_enable()
440 	iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);  in intel_ntb4_link_enable()
443 	ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);  in intel_ntb4_link_enable()
445 	iowrite32(ppd0, ndev->self_mmio + GEN4_PPD0_OFFSET);  in intel_ntb4_link_enable()
448 	ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);  in intel_ntb4_link_enable()
454 	ndev->dev_up = 1;  in intel_ntb4_link_enable()
461 	struct intel_ntb_dev *ndev;  in intel_ntb4_link_disable()  local
465 	ndev = container_of(ntb, struct intel_ntb_dev, ntb);  in intel_ntb4_link_disable()
470 	ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);  in intel_ntb4_link_disable()
473 	iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl);  in intel_ntb4_link_disable()
475 	lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);  in intel_ntb4_link_disable()
477 	iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);  in intel_ntb4_link_disable()
479 	ndev->dev_up = 0;  in intel_ntb4_link_disable()
489 	struct intel_ntb_dev *ndev = ntb_ndev(ntb);  in intel_ntb4_mw_get_align()  local
496 	if (idx >= ndev->b2b_idx && !ndev->b2b_off)  in intel_ntb4_mw_get_align()
499 	bar = ndev_mw_to_bar(ndev, idx);  in intel_ntb4_mw_get_align()
503 	bar_size = pci_resource_len(ndev->ntb.pdev, bar);  in intel_ntb4_mw_get_align()
505 	if (idx == ndev->b2b_idx)  in intel_ntb4_mw_get_align()
506 		mw_size = bar_size - ndev->b2b_off;  in intel_ntb4_mw_get_align()
511 		if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN)  in intel_ntb4_mw_get_align()
512 			*addr_align = pci_resource_len(ndev->ntb.pdev, bar);  in intel_ntb4_mw_get_align()