Lines Matching +full:0 +full:x308
34 #define FLASH_SIZE_ADDR 0x04000016
35 #define PING_BUFFER_ADDRESS 0x19000
36 #define PONG_BUFFER_ADDRESS 0x1a000
37 #define SWBL_REGIN 0x41050034
38 #define SWBL_REGOUT 0x4105003c
39 #define PING_WRITE 0x1
40 #define PONG_WRITE 0x2
45 #define REGIN_VALID 0xA
46 #define REGIN_INPUT 0xA0
47 #define REGOUT_VALID 0xAB
48 #define REGOUT_INVALID (~0xAB)
49 #define CMD_PASS 0xAA
50 #define CMD_FAIL 0xCC
66 #define RSI_ULP_RESET_REG 0x161
67 #define RSI_WATCH_DOG_TIMER_1 0x16c
68 #define RSI_WATCH_DOG_TIMER_2 0x16d
69 #define RSI_WATCH_DOG_DELAY_TIMER_1 0x16e
70 #define RSI_WATCH_DOG_DELAY_TIMER_2 0x16f
71 #define RSI_WATCH_DOG_TIMER_ENABLE 0x170
74 #define NWP_AHB_BASE_ADDR 0x41300000
75 #define NWP_WWD_INTERRUPT_TIMER (NWP_AHB_BASE_ADDR + 0x300)
76 #define NWP_WWD_SYSTEM_RESET_TIMER (NWP_AHB_BASE_ADDR + 0x304)
77 #define NWP_WWD_WINDOW_TIMER (NWP_AHB_BASE_ADDR + 0x308)
78 #define NWP_WWD_TIMER_SETTINGS (NWP_AHB_BASE_ADDR + 0x30C)
79 #define NWP_WWD_MODE_AND_RSTART (NWP_AHB_BASE_ADDR + 0x310)
80 #define NWP_WWD_RESET_BYPASS (NWP_AHB_BASE_ADDR + 0x314)
81 #define NWP_FSM_INTR_MASK_REG (NWP_AHB_BASE_ADDR + 0x104)
86 #define NWP_WWD_TIMER_DISABLE 0xAA0001
95 #define RSI_ULP_TIMER_ENABLE ((0xaa000) | RSI_RESTART_WDT | \
97 #define RSI_RF_SPI_PROG_REG_BASE_ADDR 0x40080000
100 #define RSI_GSPI_CTRL_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
101 #define RSI_GSPI_DATA_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
102 #define RSI_GSPI_DATA_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
103 #define RSI_GSPI_DATA_REG2 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
105 #define RSI_GSPI_CTRL_REG0_VALUE 0x340
121 #define COMMON_HAL_CARD_READY_IND 0x0
128 #define BBP_INFO_40MHZ 0x6
130 #define FW_FLASH_OFFSET 0x820
131 #define LMAC_VER_OFFSET_9113 (FW_FLASH_OFFSET + 0x200)
132 #define LMAC_VER_OFFSET_9116 0x22C2
137 #define RSI_9116_FW_MAGIC_WORD 0x5aa5
139 #define MEM_ACCESS_CTRL_FROM_HOST 0x41300000
157 #define RSI_BL_CTRL_LEN_MASK 0xFFFFFF