Lines Matching +full:0 +full:x51
41 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8822b_read_efuse()
42 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8822b_read_efuse()
44 efuse->country_code[0] = map->country_code[0]; in rtw8822b_read_efuse()
47 efuse->regd = map->rf_board_option & 0x7; in rtw8822b_read_efuse()
51 for (i = 0; i < 4; i++) in rtw8822b_read_efuse()
63 return 0; in rtw8822b_read_efuse()
69 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
70 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); in rtw8822b_phy_rfe_init()
71 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
74 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); in rtw8822b_phy_rfe_init()
75 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
78 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); in rtw8822b_phy_rfe_init()
79 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
84 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
85 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
86 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
87 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
92 u8 i = 0; in rtw8822b_get_swing_index()
95 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); in rtw8822b_get_swing_index()
96 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { in rtw8822b_get_swing_index()
118 dm_info->delta_power_index[path] = 0; in rtw8822b_pwrtrack_init()
129 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8822b_phy_bf_init()
150 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8822b_phy_set_param()
151 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); in rtw8822b_phy_set_param()
152 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); in rtw8822b_phy_set_param()
168 #define WLAN_SLOT_TIME 0x09
169 #define WLAN_PIFS_TIME 0x19
170 #define WLAN_SIFS_CCK_CONT_TX 0xA
171 #define WLAN_SIFS_OFDM_CONT_TX 0xE
172 #define WLAN_SIFS_CCK_TRX 0x10
173 #define WLAN_SIFS_OFDM_TRX 0x10
174 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
175 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
176 #define WLAN_RDG_NAV 0x05
177 #define WLAN_TXOP_NAV 0x1B
178 #define WLAN_CCK_RX_TSF 0x30
179 #define WLAN_OFDM_RX_TSF 0x30
180 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
181 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
182 #define WLAN_DRV_EARLY_INT 0x04
183 #define WLAN_BCN_DMA_TIME 0x02
185 #define WLAN_RX_FILTER0 0x0FFFFFFF
186 #define WLAN_RX_FILTER2 0xFFFF
187 #define WLAN_RCR_CFG 0xE400220E
191 #define WLAN_AMPDU_MAX_TIME 0x70
192 #define WLAN_RTS_LEN_TH 0xFF
193 #define WLAN_RTS_TX_TIME_TH 0x08
194 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
195 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
196 #define FAST_EDCA_VO_TH 0x06
197 #define FAST_EDCA_VI_TH 0x06
198 #define FAST_EDCA_BE_TH 0x06
199 #define FAST_EDCA_BK_TH 0x06
200 #define WLAN_BAR_RETRY_LIMIT 0x01
201 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
203 #define WLAN_TX_FUNC_CFG1 0x30
204 #define WLAN_TX_FUNC_CFG2 0x30
205 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
206 #define WLAN_MAC_OPT_LB_FUNC1 0x80
207 #define WLAN_MAC_OPT_FUNC2 0x30810041
240 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); in rtw8822b_mac_init()
265 return 0; in rtw8822b_mac_init()
273 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); in rtw8822b_set_channel_rfe_efem()
274 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_efem()
275 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); in rtw8822b_set_channel_rfe_efem()
277 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); in rtw8822b_set_channel_rfe_efem()
278 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_efem()
279 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); in rtw8822b_set_channel_rfe_efem()
282 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_efem()
287 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_efem()
290 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_efem()
293 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_efem()
303 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); in rtw8822b_set_channel_rfe_ifem()
304 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_ifem()
307 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); in rtw8822b_set_channel_rfe_ifem()
308 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_ifem()
311 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_ifem()
317 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_ifem()
320 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_ifem()
323 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_ifem()
326 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); in rtw8822b_set_channel_rfe_ifem()
345 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
346 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
347 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
351 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
352 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
353 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
357 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
358 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
359 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
454 reg830 = 0x79a0ea28; in rtw8822b_set_channel_cca()
462 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); in rtw8822b_set_channel_cca()
465 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); in rtw8822b_set_channel_cca()
468 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
469 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
470 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
471 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
472 0x6, 0x5, 0x0, 0x0, 0x7};
473 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
474 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
479 #define RF18_BAND_2G (0) in rtw8822b_set_channel_rf()
494 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822b_set_channel_rf()
522 rf_reg_be = 0x0; in rtw8822b_set_channel_rf()
534 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ in rtw8822b_set_channel_rf()
536 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); in rtw8822b_set_channel_rf()
538 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); in rtw8822b_set_channel_rf()
540 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
542 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
544 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8822b_set_channel_rf()
558 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); in rtw8822b_toggle_igi()
559 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); in rtw8822b_toggle_igi()
560 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); in rtw8822b_toggle_igi()
561 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); in rtw8822b_toggle_igi()
562 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); in rtw8822b_toggle_igi()
564 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); in rtw8822b_toggle_igi()
573 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
574 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); in rtw8822b_set_channel_rxdfir()
575 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
578 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
579 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
580 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
583 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
584 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
585 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8822b_set_channel_rxdfir()
597 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
598 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8822b_set_channel_bb()
599 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8822b_set_channel_bb()
600 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8822b_set_channel_bb()
602 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); in rtw8822b_set_channel_bb()
603 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8822b_set_channel_bb()
605 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); in rtw8822b_set_channel_bb()
606 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8822b_set_channel_bb()
608 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); in rtw8822b_set_channel_bb()
609 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); in rtw8822b_set_channel_bb()
612 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); in rtw8822b_set_channel_bb()
614 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8822b_set_channel_bb()
615 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8822b_set_channel_bb()
616 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
617 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); in rtw8822b_set_channel_bb()
620 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); in rtw8822b_set_channel_bb()
622 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); in rtw8822b_set_channel_bb()
624 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); in rtw8822b_set_channel_bb()
627 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8822b_set_channel_bb()
629 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8822b_set_channel_bb()
631 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8822b_set_channel_bb()
633 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8822b_set_channel_bb()
635 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); in rtw8822b_set_channel_bb()
642 val32 &= 0xFFCFFC00; in rtw8822b_set_channel_bb()
646 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
655 val32 &= 0xFF3FF300; in rtw8822b_set_channel_bb()
656 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); in rtw8822b_set_channel_bb()
659 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
663 val32 &= 0xFCEFCF00; in rtw8822b_set_channel_bb()
664 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); in rtw8822b_set_channel_bb()
667 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
670 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); in rtw8822b_set_channel_bb()
671 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); in rtw8822b_set_channel_bb()
676 val32 &= 0xEFEEFE00; in rtw8822b_set_channel_bb()
680 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
681 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
685 val32 &= 0xEFFEFF00; in rtw8822b_set_channel_bb()
689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
690 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
732 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
734 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
737 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
739 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
741 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); in rtw8822b_config_trx_mode()
742 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); in rtw8822b_config_trx_mode()
743 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); in rtw8822b_config_trx_mode()
746 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); in rtw8822b_config_trx_mode()
747 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); in rtw8822b_config_trx_mode()
749 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); in rtw8822b_config_trx_mode()
750 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); in rtw8822b_config_trx_mode()
754 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); in rtw8822b_config_trx_mode()
756 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); in rtw8822b_config_trx_mode()
763 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); in rtw8822b_config_trx_mode()
764 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); in rtw8822b_config_trx_mode()
768 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); in rtw8822b_config_trx_mode()
769 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); in rtw8822b_config_trx_mode()
772 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); in rtw8822b_config_trx_mode()
774 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); in rtw8822b_config_trx_mode()
780 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); in rtw8822b_config_trx_mode()
781 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); in rtw8822b_config_trx_mode()
782 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); in rtw8822b_config_trx_mode()
784 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); in rtw8822b_config_trx_mode()
785 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); in rtw8822b_config_trx_mode()
786 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); in rtw8822b_config_trx_mode()
789 for (counter = 100; counter > 0; counter--) { in rtw8822b_config_trx_mode()
792 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
793 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
796 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); in rtw8822b_config_trx_mode()
798 if (rf_reg33 == 0x00001) in rtw8822b_config_trx_mode()
802 if (WARN(counter <= 0, "write RF mode table fail\n")) in rtw8822b_config_trx_mode()
805 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
806 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
807 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); in rtw8822b_config_trx_mode()
808 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); in rtw8822b_config_trx_mode()
809 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
810 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
840 u8 evm_dbm = 0; in query_phy_status_page1()
877 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
885 if (rx_evm < 0) { in query_phy_status_page1()
887 evm_dbm = 0; in query_phy_status_page1()
900 page = *phy_status & 0xf; in query_phy_status()
903 case 0: in query_phy_status()
923 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8822b_query_rx_desc()
960 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8822b_set_tx_power_index_by_rate()
965 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8822b_set_tx_power_index_by_rate()
968 shift = rate & 0x3; in rtw8822b_set_tx_power_index_by_rate()
970 if (shift == 0x3) { in rtw8822b_set_tx_power_index_by_rate()
971 rate_idx = rate & 0xfc; in rtw8822b_set_tx_power_index_by_rate()
974 phy_pwr_idx = 0; in rtw8822b_set_tx_power_index_by_rate()
984 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822b_set_tx_power_index()
985 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) in rtw8822b_set_tx_power_index()
1008 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", in rtw8822b_set_antenna()
1012 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); in rtw8822b_set_antenna()
1017 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); in rtw8822b_set_antenna()
1026 return 0; in rtw8822b_set_antenna()
1047 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); in rtw8822b_false_alarm_statistics()
1048 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); in rtw8822b_false_alarm_statistics()
1049 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); in rtw8822b_false_alarm_statistics()
1054 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822b_false_alarm_statistics()
1056 crc32_cnt = rtw_read32(rtwdev, 0xf04); in rtw8822b_false_alarm_statistics()
1057 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1058 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1059 crc32_cnt = rtw_read32(rtwdev, 0xf14); in rtw8822b_false_alarm_statistics()
1060 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1061 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1062 crc32_cnt = rtw_read32(rtwdev, 0xf10); in rtw8822b_false_alarm_statistics()
1063 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1064 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1065 crc32_cnt = rtw_read32(rtwdev, 0xf0c); in rtw8822b_false_alarm_statistics()
1066 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1067 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1069 cca32_cnt = rtw_read32(rtwdev, 0xf08); in rtw8822b_false_alarm_statistics()
1070 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822b_false_alarm_statistics()
1073 cca32_cnt = rtw_read32(rtwdev, 0xfcc); in rtw8822b_false_alarm_statistics()
1074 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1078 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1079 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1080 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1081 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1082 rtw_write32_set(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1083 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1089 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8822b_do_iqk()
1096 for (counter = 0; counter < 300; counter++) { in rtw8822b_do_iqk()
1098 if (rf_reg == 0xabcde) in rtw8822b_do_iqk()
1102 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8822b_do_iqk()
1105 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8822b_do_iqk()
1107 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8822b_do_iqk()
1122 /* 0x790[5:0]=0x5 */ in rtw8822b_coex_cfg_init()
1123 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); in rtw8822b_coex_cfg_init()
1126 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8822b_coex_cfg_init()
1147 u8 regval = 0; in rtw8822b_coex_cfg_ant_switch()
1163 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1164 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1165 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1166 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1168 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); in rtw8822b_coex_cfg_ant_switch()
1171 if (coex_rfe->rfe_module_type != 0x4 && in rtw8822b_coex_cfg_ant_switch()
1172 coex_rfe->rfe_module_type != 0x2) in rtw8822b_coex_cfg_ant_switch()
1173 regval = 0x3; in rtw8822b_coex_cfg_ant_switch()
1175 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1177 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1179 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8822b_coex_cfg_ant_switch()
1185 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1186 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1187 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1188 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1190 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); in rtw8822b_coex_cfg_ant_switch()
1192 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1196 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1197 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1198 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1199 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1200 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); in rtw8822b_coex_cfg_ant_switch()
1203 /* 0x4c[23] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1204 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); in rtw8822b_coex_cfg_ant_switch()
1206 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1210 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1211 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1212 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1213 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1216 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1217 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1218 /* 0x4c[24] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1219 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); in rtw8822b_coex_cfg_ant_switch()
1230 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1231 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1232 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1233 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822b_coex_cfg_gnt_debug()
1234 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1245 coex_rfe->ant_switch_polarity = 0; in rtw8822b_coex_cfg_rfe_type()
1247 if (coex_rfe->rfe_module_type == 0x12 || in rtw8822b_coex_cfg_rfe_type()
1248 coex_rfe->rfe_module_type == 0x15 || in rtw8822b_coex_cfg_rfe_type()
1249 coex_rfe->rfe_module_type == 0x16) in rtw8822b_coex_cfg_rfe_type()
1271 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); in rtw8822b_coex_cfg_rfe_type()
1272 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); in rtw8822b_coex_cfg_rfe_type()
1273 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); in rtw8822b_coex_cfg_rfe_type()
1276 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); in rtw8822b_coex_cfg_rfe_type()
1279 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1282 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1289 static const u16 reg_addr[] = {0xc58, 0xe58}; in rtw8822b_coex_cfg_wl_tx_power()
1290 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; in rtw8822b_coex_cfg_wl_tx_power()
1303 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) in rtw8822b_coex_cfg_wl_tx_power()
1304 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); in rtw8822b_coex_cfg_wl_tx_power()
1313 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, in rtw8822b_coex_cfg_wl_rx_gain()
1314 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1315 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, in rtw8822b_coex_cfg_wl_rx_gain()
1316 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1317 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, in rtw8822b_coex_cfg_wl_rx_gain()
1318 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, in rtw8822b_coex_cfg_wl_rx_gain()
1319 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1320 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, in rtw8822b_coex_cfg_wl_rx_gain()
1321 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1326 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1327 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1328 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, in rtw8822b_coex_cfg_wl_rx_gain()
1329 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1330 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, in rtw8822b_coex_cfg_wl_rx_gain()
1331 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, in rtw8822b_coex_cfg_wl_rx_gain()
1332 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1333 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, in rtw8822b_coex_cfg_wl_rx_gain()
1334 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1344 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1348 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1349 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1350 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1351 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1353 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1354 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); in rtw8822b_coex_cfg_wl_rx_gain()
1357 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1358 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1359 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1360 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1371 u8 swing_lower_bound = 0; in rtw8822b_txagc_swing_offset()
1372 u8 max_tx_pwr_idx_offset = 0xf; in rtw8822b_txagc_swing_offset()
1373 s8 agc_index = 0; in rtw8822b_txagc_swing_offset()
1378 if (delta_pwr_idx >= 0) { in rtw8822b_txagc_swing_offset()
1396 agc_index = 0; in rtw8822b_txagc_swing_offset()
1415 reg1 = 0xc94; in rtw8822b_pwrtrack_set_pwr()
1416 reg2 = 0xc1c; in rtw8822b_pwrtrack_set_pwr()
1418 reg1 = 0xe94; in rtw8822b_pwrtrack_set_pwr()
1419 reg2 = 0xe1c; in rtw8822b_pwrtrack_set_pwr()
1482 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) in rtw8822b_phy_pwrtrack()
1485 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8822b_phy_pwrtrack()
1495 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822b_phy_pwrtrack()
1508 if (efuse->power_track_type != 0) in rtw8822b_pwr_track()
1513 GENMASK(17, 16), 0x03); in rtw8822b_pwr_track()
1554 {0x0086,
1558 RTW_PWR_CMD_WRITE, BIT(0), 0},
1559 {0x0086,
1564 {0x004A,
1568 RTW_PWR_CMD_WRITE, BIT(0), 0},
1569 {0x0005,
1573 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1574 {0x0300,
1578 RTW_PWR_CMD_WRITE, 0xFF, 0},
1579 {0x0301,
1583 RTW_PWR_CMD_WRITE, 0xFF, 0},
1584 {0xFFFF,
1587 0,
1588 RTW_PWR_CMD_END, 0, 0},
1592 {0x0012,
1596 RTW_PWR_CMD_WRITE, BIT(1), 0},
1597 {0x0012,
1601 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1602 {0x0020,
1606 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1607 {0x0001,
1612 {0x0000,
1616 RTW_PWR_CMD_WRITE, BIT(5), 0},
1617 {0x0005,
1621 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1622 {0x0075,
1626 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1627 {0x0006,
1632 {0x0075,
1636 RTW_PWR_CMD_WRITE, BIT(0), 0},
1637 {0xFF1A,
1641 RTW_PWR_CMD_WRITE, 0xFF, 0},
1642 {0x0006,
1646 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1647 {0x0005,
1651 RTW_PWR_CMD_WRITE, BIT(7), 0},
1652 {0x0005,
1656 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1657 {0x10C3,
1661 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1662 {0x0005,
1666 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1667 {0x0005,
1671 RTW_PWR_CMD_POLLING, BIT(0), 0},
1672 {0x0020,
1677 {0x10A8,
1681 RTW_PWR_CMD_WRITE, 0xFF, 0},
1682 {0x10A9,
1686 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1687 {0x10AA,
1691 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1692 {0x0068,
1697 {0x0029,
1701 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1702 {0x0024,
1706 RTW_PWR_CMD_WRITE, BIT(2), 0},
1707 {0x0074,
1712 {0x00AF,
1717 {0xFFFF,
1720 0,
1721 RTW_PWR_CMD_END, 0, 0},
1725 {0x0003,
1729 RTW_PWR_CMD_WRITE, BIT(2), 0},
1730 {0x0093,
1734 RTW_PWR_CMD_WRITE, BIT(3), 0},
1735 {0x001F,
1739 RTW_PWR_CMD_WRITE, 0xFF, 0},
1740 {0x00EF,
1744 RTW_PWR_CMD_WRITE, 0xFF, 0},
1745 {0xFF1A,
1749 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1750 {0x0049,
1754 RTW_PWR_CMD_WRITE, BIT(1), 0},
1755 {0x0006,
1759 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1760 {0x0002,
1764 RTW_PWR_CMD_WRITE, BIT(1), 0},
1765 {0x10C3,
1769 RTW_PWR_CMD_WRITE, BIT(0), 0},
1770 {0x0005,
1775 {0x0005,
1779 RTW_PWR_CMD_POLLING, BIT(1), 0},
1780 {0x0020,
1784 RTW_PWR_CMD_WRITE, BIT(3), 0},
1785 {0x0000,
1790 {0xFFFF,
1793 0,
1794 RTW_PWR_CMD_END, 0, 0},
1798 {0x0005,
1803 {0x0007,
1807 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1808 {0x0067,
1812 RTW_PWR_CMD_WRITE, BIT(5), 0},
1813 {0x0005,
1818 {0x004A,
1822 RTW_PWR_CMD_WRITE, BIT(0), 0},
1823 {0x0067,
1827 RTW_PWR_CMD_WRITE, BIT(5), 0},
1828 {0x0067,
1832 RTW_PWR_CMD_WRITE, BIT(4), 0},
1833 {0x004F,
1837 RTW_PWR_CMD_WRITE, BIT(0), 0},
1838 {0x0067,
1842 RTW_PWR_CMD_WRITE, BIT(1), 0},
1843 {0x0046,
1848 {0x0067,
1852 RTW_PWR_CMD_WRITE, BIT(2), 0},
1853 {0x0046,
1858 {0x0062,
1863 {0x0081,
1867 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1868 {0x0005,
1873 {0x0086,
1877 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1878 {0x0086,
1882 RTW_PWR_CMD_POLLING, BIT(1), 0},
1883 {0x0090,
1887 RTW_PWR_CMD_WRITE, BIT(1), 0},
1888 {0x0044,
1892 RTW_PWR_CMD_WRITE, 0xFF, 0},
1893 {0x0040,
1897 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1898 {0x0041,
1902 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1903 {0x0042,
1907 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1908 {0xFFFF,
1911 0,
1912 RTW_PWR_CMD_END, 0, 0},
1928 {0xFFFF, 0x00,
1935 {0x0001, 0xA841,
1939 {0xFFFF, 0x0000,
1946 {0x0001, 0xA841,
1950 {0x0002, 0x60C6,
1954 {0x0008, 0x3596,
1958 {0x0009, 0x321C,
1962 {0x000A, 0x9623,
1966 {0x0020, 0x94FF,
1970 {0x0021, 0xFFCF,
1974 {0x0026, 0xC006,
1978 {0x0029, 0xFF0E,
1982 {0x002A, 0x1840,
1986 {0xFFFF, 0x0000,
1993 {0x0001, 0xA841,
1997 {0x0002, 0x60C6,
2001 {0x0008, 0x3597,
2005 {0x0009, 0x321C,
2009 {0x000A, 0x9623,
2013 {0x0020, 0x94FF,
2017 {0x0021, 0xFFCF,
2021 {0x0026, 0xC006,
2025 {0x0029, 0xFF0E,
2029 {0x002A, 0x3040,
2033 {0xFFFF, 0x0000,
2052 [3] = RTW_DEF_RFE(8822b, 3, 0),
2057 [0] = { .addr = 0xc50, .mask = 0x7f },
2058 [1] = { .addr = 0xe50, .mask = 0x7f },
2070 {64, 64, 0, 0, 1},
2071 {64, 64, 64, 0, 1},
2138 {0xffffffff, 0xffffffff}, /* case-0 */
2139 {0x55555555, 0x55555555},
2140 {0x66555555, 0x66555555},
2141 {0xaaaaaaaa, 0xaaaaaaaa},
2142 {0x5a5a5a5a, 0x5a5a5a5a},
2143 {0xfafafafa, 0xfafafafa}, /* case-5 */
2144 {0x6a5a6a5a, 0xaaaaaaaa},
2145 {0x6a5a56aa, 0x6a5a56aa},
2146 {0x6a5a5a5a, 0x6a5a5a5a},
2147 {0x66555555, 0x5a5a5a5a},
2148 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2149 {0x66555555, 0xfafafafa},
2150 {0x66555555, 0x5a5a5aaa},
2151 {0x66555555, 0x5aaa5aaa},
2152 {0x66555555, 0xaaaa5aaa},
2153 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2154 {0xffff55ff, 0xfafafafa},
2155 {0xffff55ff, 0x6afa5afa},
2156 {0xaaffffaa, 0xfafafafa},
2157 {0xaa5555aa, 0x5a5a5a5a},
2158 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2159 {0xaa5555aa, 0xaaaaaaaa},
2160 {0xffffffff, 0x5a5a5a5a},
2161 {0xffffffff, 0x6a5a5a5a},
2162 {0xffffffff, 0x55555555},
2163 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2164 {0x55555555, 0x5a5a5a5a},
2165 {0x55555555, 0xaaaaaaaa},
2166 {0x55555555, 0x6a5a6a5a},
2167 {0x66556655, 0x66556655}
2172 {0xffffffff, 0xffffffff}, /* case-100 */
2173 {0x55555555, 0x55555555},
2174 {0x66555555, 0x66555555},
2175 {0xaaaaaaaa, 0xaaaaaaaa},
2176 {0x5a5a5a5a, 0x5a5a5a5a},
2177 {0xfafafafa, 0xfafafafa}, /* case-105 */
2178 {0x5afa5afa, 0x5afa5afa},
2179 {0x55555555, 0xfafafafa},
2180 {0x66555555, 0xfafafafa},
2181 {0x66555555, 0x5a5a5a5a},
2182 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2183 {0x66555555, 0xaaaaaaaa},
2184 {0xffff55ff, 0xfafafafa},
2185 {0xffff55ff, 0x5afa5afa},
2186 {0xffff55ff, 0xaaaaaaaa},
2187 {0xaaffffaa, 0xfafafafa}, /* case-115 */
2188 {0xaaffffaa, 0x5afa5afa},
2189 {0xaaffffaa, 0xaaaaaaaa},
2190 {0xffffffff, 0xfafafafa},
2191 {0xffffffff, 0x5afa5afa},
2192 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2193 {0x55ff55ff, 0x5afa5afa},
2194 {0x55ff55ff, 0xaaaaaaaa},
2195 {0x55ff55ff, 0x55ff55ff}
2200 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2201 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2202 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2203 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2204 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2205 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2206 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2207 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2208 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2209 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2210 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2211 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2212 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2213 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2214 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2215 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2216 { {0x51, 0x45, 0x03, 0x10, 0x10} },
2217 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2218 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2219 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2220 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2221 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2222 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2223 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2224 { {0x65, 0x10, 0x03, 0x11, 0x11} },
2225 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2226 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2227 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2232 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2233 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2234 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2235 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2236 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2237 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2238 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2239 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2240 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2241 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2242 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2243 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2244 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2245 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2246 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2247 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2248 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2249 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2250 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2251 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2252 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
2258 static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} };
2262 {0, 0, false, 7}, /* for normal */
2263 {0, 16, false, 7}, /* for WL-CPT */
2264 {4, 0, true, 1},
2271 {0, 0, false, 7}, /* for normal */
2272 {0, 16, false, 7}, /* for WL-CPT */
2273 {4, 0, true, 1},
2283 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2286 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2289 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2296 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2299 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2302 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2309 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2312 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2315 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2322 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2325 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2328 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2334 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2340 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2346 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2352 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2358 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2364 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2370 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2376 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2405 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2406 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2407 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2408 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2409 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2410 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2411 {0, 0, RTW_REG_DOMAIN_NL},
2412 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2413 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2414 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2415 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2416 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2417 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2418 {0, 0, RTW_REG_DOMAIN_NL},
2419 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2420 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2421 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2422 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2423 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2424 {0, 0, RTW_REG_DOMAIN_NL},
2425 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2426 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2427 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2428 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2448 .max_power_index = 0x3f,
2449 .csi_buf_pg_num = 0,
2452 .dig_min = 0x1c,
2456 .sys_func_en = 0xDC,
2465 .rf_base_addr = {0x2800, 0x2c00},
2466 .rf_sipi_addr = {0xc90, 0xe90},
2480 .coex_para_ver = 0x20070206,
2481 .bt_desired_ver = 0x6,
2501 .bt_afh_span_bw20 = 0x24,
2502 .bt_afh_span_bw40 = 0x36,
2509 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},