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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
9 * Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
11 * 0: POFF--Power Off
12 * 1: PDN--Power Down
13 * 2: CARDEMU--Card Emulation
14 * 3: ACT--Active Mode
15 * 4: LPS--Low Power State
16 * 5: SUS--Suspend
37 #define RTL8723B_TRANS_END_STEPS 1
43 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
50 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
51 /*Delay 1ms*/ \
54 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
55 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
64 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
65 /* wait till 0x04[17] = 1 power ready*/ \
67 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
71 /* release WLON reset 0x04[16]=1*/ \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
84 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
87 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
90 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
102 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
108 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
120 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
123 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
124 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
126 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
129 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
133 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
136 PWR_CMD_WRITE, BIT(5), BIT(5)}, \
137 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
140 PWR_CMD_WRITE, BIT(0), 0},
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
152 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
153 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
164 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
167 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
178 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
181 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
182 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
184 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
187 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
200 /*0x04[10] = 1, enable SW LPS*/ \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
203 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
206 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
208 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
211 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
214 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
222 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
225 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
228 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
231 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
234 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
235 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
237 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
246 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
255 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
256 /* 0x04[15] = 1*/ \
258 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
293 /*Delay 1us*/ \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
304 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
330 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
333 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
336 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
337 /*. 0x101[1] = 1*/ \
339 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
343 /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
345 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \