Lines Matching +full:0 +full:x000fc000
73 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); in rtl92se_set_hw_reg()
74 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); in rtl92se_set_hw_reg()
78 u16 rate_cfg = ((u16 *) val)[0]; in rtl92se_set_hw_reg()
79 u8 rate_index = 0; in rtl92se_set_hw_reg()
82 rate_cfg = rate_cfg & 0x150; in rtl92se_set_hw_reg()
84 rate_cfg = rate_cfg & 0x15f; in rtl92se_set_hw_reg()
86 rate_cfg |= 0x01; in rtl92se_set_hw_reg()
88 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff); in rtl92se_set_hw_reg()
90 (rate_cfg >> 8) & 0xff); in rtl92se_set_hw_reg()
92 while (rate_cfg > 0x1) { in rtl92se_set_hw_reg()
101 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); in rtl92se_set_hw_reg()
103 ((u16 *)(val + 4))[0]); in rtl92se_set_hw_reg()
107 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]); in rtl92se_set_hw_reg()
115 "HW_VAR_SLOT_TIME %x\n", val[0]); in rtl92se_set_hw_reg()
117 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]); in rtl92se_set_hw_reg()
119 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { in rtl92se_set_hw_reg()
131 reg_tmp |= 0x80; in rtl92se_set_hw_reg()
144 sec_min_space = 0; in rtl92se_set_hw_reg()
154 ((mac->min_space_cfg & 0xf8) | in rtl92se_set_hw_reg()
190 15, 15, 15, 15, 0}; in rtl92se_set_hw_reg()
191 u8 index = 0; in rtl92se_set_hw_reg()
196 if (factor_toset > 0xf) in rtl92se_set_hw_reg()
197 factor_toset = 0xf; in rtl92se_set_hw_reg()
199 for (index = 0; index < 17; index++) { in rtl92se_set_hw_reg()
205 for (index = 0; index < 8; index++) { in rtl92se_set_hw_reg()
237 mac->ac[0].aifs)); in rtl92se_set_hw_reg()
242 0x0 : 0x1); in rtl92se_set_hw_reg()
280 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl); in rtl92se_set_hw_reg()
285 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); in rtl92se_set_hw_reg()
286 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92se_set_hw_reg()
290 u8 retry_limit = val[0]; in rtl92se_set_hw_reg()
336 u8 u1bdata = 0; in rtl92se_set_hw_reg()
340 MASKBYTE0, 0x33); in rtl92se_set_hw_reg()
346 ((u1bdata & 0xf0) | 0x03)); in rtl92se_set_hw_reg()
352 (u1bdata | 0x04)); in rtl92se_set_hw_reg()
358 MASKBYTE0, 0x13); in rtl92se_set_hw_reg()
364 ((u1bdata & 0xf0) | 0x01)); in rtl92se_set_hw_reg()
369 MASKBYTE1, (u1bdata & 0xfb)); in rtl92se_set_hw_reg()
383 rpwm_val = 0x02; /* RF off */ in rtl92se_set_hw_reg()
395 rpwm_val = 0x0C; /* RF on */ in rtl92se_set_hw_reg()
418 u8 sec_reg_value = 0x0; in rtl92se_enable_hw_security_config()
463 tmpvalue = 0; in _rtl92se_halset_sysclk()
473 if (waitcount == 0) in _rtl92se_halset_sysclk()
479 if (waitcount == 0) in _rtl92se_halset_sysclk()
542 tmpu1b &= 0xFE; in _rtl92se_macconfig_before_fwdownload()
545 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0)); in _rtl92se_macconfig_before_fwdownload()
558 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); in _rtl92se_macconfig_before_fwdownload()
560 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); in _rtl92se_macconfig_before_fwdownload()
564 rtl_write_byte(rtlpriv, RPWM, 0x0); in _rtl92se_macconfig_before_fwdownload()
568 tmpu1b &= 0x73; in _rtl92se_macconfig_before_fwdownload()
573 rtl_write_byte(rtlpriv, CMDR, 0); in _rtl92se_macconfig_before_fwdownload()
574 rtl_write_byte(rtlpriv, TCR, 0); in _rtl92se_macconfig_before_fwdownload()
576 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ in _rtl92se_macconfig_before_fwdownload()
577 tmpu1b = rtl_read_byte(rtlpriv, 0x562); in _rtl92se_macconfig_before_fwdownload()
578 tmpu1b |= 0x08; in _rtl92se_macconfig_before_fwdownload()
579 rtl_write_byte(rtlpriv, 0x562, tmpu1b); in _rtl92se_macconfig_before_fwdownload()
581 rtl_write_byte(rtlpriv, 0x562, tmpu1b); in _rtl92se_macconfig_before_fwdownload()
585 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); in _rtl92se_macconfig_before_fwdownload()
589 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); in _rtl92se_macconfig_before_fwdownload()
593 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); in _rtl92se_macconfig_before_fwdownload()
598 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); in _rtl92se_macconfig_before_fwdownload()
603 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); in _rtl92se_macconfig_before_fwdownload()
613 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); in _rtl92se_macconfig_before_fwdownload()
619 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); in _rtl92se_macconfig_before_fwdownload()
623 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | in _rtl92se_macconfig_before_fwdownload()
626 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); in _rtl92se_macconfig_before_fwdownload()
631 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); in _rtl92se_macconfig_before_fwdownload()
635 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); in _rtl92se_macconfig_before_fwdownload()
660 rtl_write_word(rtlpriv, CMDR, 0x07FC); in _rtl92se_macconfig_before_fwdownload()
665 rtl_write_byte(rtlpriv, 0x6, 0x30); in _rtl92se_macconfig_before_fwdownload()
666 rtl_write_byte(rtlpriv, 0x49, 0xf0); in _rtl92se_macconfig_before_fwdownload()
668 rtl_write_byte(rtlpriv, 0x4b, 0x81); in _rtl92se_macconfig_before_fwdownload()
670 rtl_write_byte(rtlpriv, 0xb5, 0x21); in _rtl92se_macconfig_before_fwdownload()
672 rtl_write_byte(rtlpriv, 0xdc, 0xff); in _rtl92se_macconfig_before_fwdownload()
673 rtl_write_byte(rtlpriv, 0xdd, 0xff); in _rtl92se_macconfig_before_fwdownload()
674 rtl_write_byte(rtlpriv, 0xde, 0xff); in _rtl92se_macconfig_before_fwdownload()
675 rtl_write_byte(rtlpriv, 0xdf, 0xff); in _rtl92se_macconfig_before_fwdownload()
677 rtl_write_byte(rtlpriv, 0x11a, 0x00); in _rtl92se_macconfig_before_fwdownload()
678 rtl_write_byte(rtlpriv, 0x11b, 0x00); in _rtl92se_macconfig_before_fwdownload()
680 for (i = 0; i < 32; i++) in _rtl92se_macconfig_before_fwdownload()
681 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b); in _rtl92se_macconfig_before_fwdownload()
683 rtl_write_byte(rtlpriv, 0x236, 0xff); in _rtl92se_macconfig_before_fwdownload()
685 rtl_write_byte(rtlpriv, 0x503, 0x22); in _rtl92se_macconfig_before_fwdownload()
688 rtl_write_byte(rtlpriv, 0x560, 0x40); in _rtl92se_macconfig_before_fwdownload()
690 rtl_write_byte(rtlpriv, 0x560, 0x00); in _rtl92se_macconfig_before_fwdownload()
692 rtl_write_byte(rtlpriv, DBG_PORT, 0x91); in _rtl92se_macconfig_before_fwdownload()
709 rtl_write_word(rtlpriv, CMDR, 0x37FC); in _rtl92se_macconfig_before_fwdownload()
721 if (pollingcnt <= 0) { in _rtl92se_macconfig_before_fwdownload()
733 (ppsc->rfoff_reason == 0)) { in _rtl92se_macconfig_before_fwdownload()
752 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */ in _rtl92se_macconfig_after_fwdownload()
754 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */ in _rtl92se_macconfig_after_fwdownload()
755 /* Turn on 0x40 Command register */ in _rtl92se_macconfig_after_fwdownload()
767 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */ in _rtl92se_macconfig_after_fwdownload()
769 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */ in _rtl92se_macconfig_after_fwdownload()
772 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a); in _rtl92se_macconfig_after_fwdownload()
773 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010); in _rtl92se_macconfig_after_fwdownload()
776 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40); in _rtl92se_macconfig_after_fwdownload()
782 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */ in _rtl92se_macconfig_after_fwdownload()
786 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */ in _rtl92se_macconfig_after_fwdownload()
791 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */ in _rtl92se_macconfig_after_fwdownload()
800 rtl_write_byte(rtlpriv, RRSR, 0xf0); in _rtl92se_macconfig_after_fwdownload()
802 rtl_write_byte(rtlpriv, RRSR, 0xff); in _rtl92se_macconfig_after_fwdownload()
803 rtl_write_byte(rtlpriv, RRSR + 1, 0x01); in _rtl92se_macconfig_after_fwdownload()
804 rtl_write_byte(rtlpriv, RRSR + 2, 0x00); in _rtl92se_macconfig_after_fwdownload()
808 for (i = 0; i < 8; i++) { in _rtl92se_macconfig_after_fwdownload()
811 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0); in _rtl92se_macconfig_after_fwdownload()
816 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f); in _rtl92se_macconfig_after_fwdownload()
818 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442); in _rtl92se_macconfig_after_fwdownload()
820 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7); in _rtl92se_macconfig_after_fwdownload()
822 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772); in _rtl92se_macconfig_after_fwdownload()
824 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd); in _rtl92se_macconfig_after_fwdownload()
827 rtl_write_dword(rtlpriv, DARFRC, 0x04010000); in _rtl92se_macconfig_after_fwdownload()
828 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605); in _rtl92se_macconfig_after_fwdownload()
829 rtl_write_dword(rtlpriv, RARFRC, 0x04010000); in _rtl92se_macconfig_after_fwdownload()
830 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605); in _rtl92se_macconfig_after_fwdownload()
832 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */ in _rtl92se_macconfig_after_fwdownload()
834 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF); in _rtl92se_macconfig_after_fwdownload()
836 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */ in _rtl92se_macconfig_after_fwdownload()
838 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080); in _rtl92se_macconfig_after_fwdownload()
840 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF); in _rtl92se_macconfig_after_fwdownload()
842 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07); in _rtl92se_macconfig_after_fwdownload()
844 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00); in _rtl92se_macconfig_after_fwdownload()
846 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */ in _rtl92se_macconfig_after_fwdownload()
847 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */ in _rtl92se_macconfig_after_fwdownload()
848 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */ in _rtl92se_macconfig_after_fwdownload()
849 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */ in _rtl92se_macconfig_after_fwdownload()
850 /* 13. Test mode and Debug Control Register (Offset: 0x0310 - 0x034F) */ in _rtl92se_macconfig_after_fwdownload()
868 tempval &= 0xFE; in _rtl92se_macconfig_after_fwdownload()
872 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72); in _rtl92se_macconfig_after_fwdownload()
887 u8 reg_bw_opmode = 0; in _rtl92se_hw_configure()
888 u32 reg_rrsr = 0; in _rtl92se_hw_configure()
889 u8 regtmp = 0; in _rtl92se_hw_configure()
895 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp; in _rtl92se_hw_configure()
903 rtl_write_byte(rtlpriv, MLT, 0x8f); in _rtl92se_hw_configure()
926 u8 tmp_byte = 0; in rtl92se_hw_init()
935 u8 secr_value = 0x0; in rtl92se_hw_init()
956 PMC_FSM) >> 16) & 0xF); in rtl92se_hw_init()
994 rtl_write_dword(rtlpriv, CMDR, 0x37FC); in rtl92se_hw_init()
1009 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB); in rtl92se_hw_init()
1011 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07); in rtl92se_hw_init()
1013 rtl_write_byte(rtlpriv, RF_CTRL, 0x07); in rtl92se_hw_init()
1024 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, in rtl92se_hw_init()
1025 (enum radio_path)0, in rtl92se_hw_init()
1034 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92se_hw_init()
1035 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92se_hw_init()
1048 for (i = 0; i < 6; i++) in rtl92se_hw_init()
1055 rtl_write_byte(rtlpriv, 0x4d, 0x0); in rtl92se_hw_init()
1057 if (hal_get_firmwareversion(rtlpriv) >= 0x49) { in rtl92se_hw_init()
1061 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF); in rtl92se_hw_init()
1066 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { in rtl92se_hw_init()
1069 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { in rtl92se_hw_init()
1096 for (i = 0; i < 4; i++) in rtl92se_hw_init()
1097 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); in rtl92se_hw_init()
1183 return 0; in _rtl92se_set_media_status()
1201 return 0; in rtl92se_set_network_type()
1212 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f); in rtl92se_set_qos()
1218 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322); in rtl92se_set_qos()
1221 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222); in rtl92se_set_qos()
1234 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); in rtl92se_enable_interrupt()
1235 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ in rtl92se_enable_interrupt()
1236 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); in rtl92se_enable_interrupt()
1250 rtl_write_dword(rtlpriv, INTA_MASK, 0); in rtl92se_disable_interrupt()
1251 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); in rtl92se_disable_interrupt()
1273 tmp = 0; in _rtl92s_set_sysclk()
1284 if (waitcnt == 0) in _rtl92s_set_sysclk()
1289 if (waitcnt == 0) in _rtl92s_set_sysclk()
1306 rtl_write_byte(rtlpriv, 0x560, 0x0); in _rtl92s_phy_set_rfhalt()
1310 u1btmp |= BIT(0); in _rtl92s_phy_set_rfhalt()
1312 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); in _rtl92s_phy_set_rfhalt()
1313 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); in _rtl92s_phy_set_rfhalt()
1314 rtl_write_word(rtlpriv, CMDR, 0x57FC); in _rtl92s_phy_set_rfhalt()
1316 rtl_write_word(rtlpriv, CMDR, 0x77FC); in _rtl92s_phy_set_rfhalt()
1317 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); in _rtl92s_phy_set_rfhalt()
1319 rtl_write_word(rtlpriv, CMDR, 0x37FC); in _rtl92s_phy_set_rfhalt()
1321 rtl_write_word(rtlpriv, CMDR, 0x77FC); in _rtl92s_phy_set_rfhalt()
1323 rtl_write_word(rtlpriv, CMDR, 0x57FC); in _rtl92s_phy_set_rfhalt()
1324 rtl_write_word(rtlpriv, CMDR, 0x0000); in _rtl92s_phy_set_rfhalt()
1328 u1btmp &= ~(BIT(0)); in _rtl92s_phy_set_rfhalt()
1336 * for register>0x40. After resume&MACIO reset, we need in _rtl92s_phy_set_rfhalt()
1350 rtl_write_byte(rtlpriv, 0x03, 0xF9); in _rtl92s_phy_set_rfhalt()
1354 /* if write 0xF1 disconnect_pci power in _rtl92s_phy_set_rfhalt()
1358 rtl_write_byte(rtlpriv, 0x03, 0xF9); in _rtl92s_phy_set_rfhalt()
1361 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70); in _rtl92s_phy_set_rfhalt()
1362 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68); in _rtl92s_phy_set_rfhalt()
1363 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00); in _rtl92s_phy_set_rfhalt()
1364 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); in _rtl92s_phy_set_rfhalt()
1365 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E); in _rtl92s_phy_set_rfhalt()
1403 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); in _rtl92se_power_domain_init()
1404 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); in _rtl92se_power_domain_init()
1412 tmpu1b &= 0xFB; in _rtl92se_power_domain_init()
1414 tmpu1b &= 0x73; in _rtl92se_power_domain_init()
1420 rtl_write_byte(rtlpriv, CMDR, 0); in _rtl92se_power_domain_init()
1421 rtl_write_byte(rtlpriv, TCR, 0); in _rtl92se_power_domain_init()
1423 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ in _rtl92se_power_domain_init()
1424 tmpu1b = rtl_read_byte(rtlpriv, 0x562); in _rtl92se_power_domain_init()
1425 tmpu1b |= 0x08; in _rtl92se_power_domain_init()
1426 rtl_write_byte(rtlpriv, 0x562, tmpu1b); in _rtl92se_power_domain_init()
1428 rtl_write_byte(rtlpriv, 0x562, tmpu1b); in _rtl92se_power_domain_init()
1432 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); in _rtl92se_power_domain_init()
1436 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); in _rtl92se_power_domain_init()
1440 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); in _rtl92se_power_domain_init()
1445 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); in _rtl92se_power_domain_init()
1450 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); in _rtl92se_power_domain_init()
1461 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); in _rtl92se_power_domain_init()
1465 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); in _rtl92se_power_domain_init()
1468 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); in _rtl92se_power_domain_init()
1472 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); in _rtl92se_power_domain_init()
1495 rtl_write_word(rtlpriv, CMDR, 0x37FC); in _rtl92se_power_domain_init()
1544 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92se_interrupt_recognized()
1555 u16 bcntime_cfg = 0; in rtl92se_set_beacon_related_registers()
1556 u16 bcn_cw = 6, bcn_ifs = 0xf; in rtl92se_set_beacon_related_registers()
1612 rtlpci->irq_mask[0] |= add_msr; in rtl92se_update_interrupt_mask()
1615 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92se_update_interrupt_mask()
1634 if (efuse_id == 0xfe) in _rtl8192se_get_ic_inferiority()
1665 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], in _rtl92se_read_adapter_info()
1671 eeprom_id = *((u16 *)&hwinfo[0]); in _rtl92se_read_adapter_info()
1687 /* VID, DID SE 0xA-D */ in _rtl92se_read_adapter_info()
1695 "EEPROMId = 0x%4x\n", eeprom_id); in _rtl92se_read_adapter_info()
1697 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); in _rtl92se_read_adapter_info()
1699 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); in _rtl92se_read_adapter_info()
1701 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); in _rtl92se_read_adapter_info()
1703 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); in _rtl92se_read_adapter_info()
1705 for (i = 0; i < 6; i += 2) { in _rtl92se_read_adapter_info()
1710 for (i = 0; i < 6; i++) in _rtl92se_read_adapter_info()
1718 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92se_read_adapter_info()
1719 for (i = 0; i < 3; i++) { in _rtl92se_read_adapter_info()
1735 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92se_read_adapter_info()
1736 for (i = 0; i < 3; i++) in _rtl92se_read_adapter_info()
1738 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", in _rtl92se_read_adapter_info()
1742 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92se_read_adapter_info()
1743 for (i = 0; i < 3; i++) in _rtl92se_read_adapter_info()
1745 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", in _rtl92se_read_adapter_info()
1749 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92se_read_adapter_info()
1750 for (i = 0; i < 3; i++) in _rtl92se_read_adapter_info()
1752 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", in _rtl92se_read_adapter_info()
1757 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92se_read_adapter_info()
1760 for (i = 0; i < 14; i++) { in _rtl92se_read_adapter_info()
1763 index = 0; in _rtl92se_read_adapter_info()
1784 for (i = 0; i < 14; i++) { in _rtl92se_read_adapter_info()
1786 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", in _rtl92se_read_adapter_info()
1794 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92se_read_adapter_info()
1795 for (i = 0; i < 3; i++) { in _rtl92se_read_adapter_info()
1802 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92se_read_adapter_info()
1804 for (i = 0; i < 14; i++) { in _rtl92se_read_adapter_info()
1807 index = 0; in _rtl92se_read_adapter_info()
1817 0xf); in _rtl92se_read_adapter_info()
1820 0xf0) >> 4); in _rtl92se_read_adapter_info()
1823 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1827 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1833 for (i = 0; i < 14; i++) { in _rtl92se_read_adapter_info()
1837 index = 0; in _rtl92se_read_adapter_info()
1845 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff; in _rtl92se_read_adapter_info()
1846 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); in _rtl92se_read_adapter_info()
1848 ((tempval >> 4) & 0xF); in _rtl92se_read_adapter_info()
1853 index = 0; in _rtl92se_read_adapter_info()
1856 index = 0x11; in _rtl92se_read_adapter_info()
1861 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff; in _rtl92se_read_adapter_info()
1863 (tempval & 0xF); in _rtl92se_read_adapter_info()
1865 ((tempval >> 4) & 0xF); in _rtl92se_read_adapter_info()
1868 rtlefuse->txpwr_safetyflag = (tempval & 0x01); in _rtl92se_read_adapter_info()
1871 rtlefuse->eeprom_regulatory = 0; in _rtl92se_read_adapter_info()
1873 /* BIT(0)~2 */ in _rtl92se_read_adapter_info()
1876 (hwinfo[EEPROM_REGULATORY] & 0x7); in _rtl92se_read_adapter_info()
1877 else /* BIT(0) */ in _rtl92se_read_adapter_info()
1879 (hwinfo[EEPROM_REGULATORY] & 0x1); in _rtl92se_read_adapter_info()
1882 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); in _rtl92se_read_adapter_info()
1884 for (i = 0; i < 14; i++) in _rtl92se_read_adapter_info()
1886 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1888 for (i = 0; i < 14; i++) in _rtl92se_read_adapter_info()
1890 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1892 for (i = 0; i < 14; i++) in _rtl92se_read_adapter_info()
1894 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1896 for (i = 0; i < 14; i++) in _rtl92se_read_adapter_info()
1898 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1906 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff; in _rtl92se_read_adapter_info()
1909 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; in _rtl92se_read_adapter_info()
1916 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8); in _rtl92se_read_adapter_info()
1918 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); in _rtl92se_read_adapter_info()
1920 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", in _rtl92se_read_adapter_info()
1929 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); in _rtl92se_read_adapter_info()
1931 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ in _rtl92se_read_adapter_info()
1932 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); in _rtl92se_read_adapter_info()
1946 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan); in _rtl92se_read_adapter_info()
1951 if (tempval == 0) in _rtl92se_read_adapter_info()
1963 tempval = rtl_read_byte(rtlpriv, 0x07); in _rtl92se_read_adapter_info()
1964 if (!(tempval & BIT(0))) { in _rtl92se_read_adapter_info()
1973 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n", in _rtl92se_read_adapter_info()
1984 u8 tmp_u1b = 0; in rtl92se_read_eeprom_info()
2014 u8 ratr_index = 0; in rtl92se_update_hal_rate_table()
2017 u16 shortgi_rate = 0; in rtl92se_update_hal_rate_table()
2018 u32 tmp_ratr_value = 0; in rtl92se_update_hal_rate_table()
2021 1 : 0; in rtl92se_update_hal_rate_table()
2023 1 : 0; in rtl92se_update_hal_rate_table()
2029 ratr_value = sta->supp_rates[0]; in rtl92se_update_hal_rate_table()
2031 ratr_value = 0xfff; in rtl92se_update_hal_rate_table()
2033 sta->ht_cap.mcs.rx_mask[0] << 12); in rtl92se_update_hal_rate_table()
2036 ratr_value &= 0x0000000D; in rtl92se_update_hal_rate_table()
2039 ratr_value &= 0x00000FF5; in rtl92se_update_hal_rate_table()
2045 ratr_value &= 0x0007F005; in rtl92se_update_hal_rate_table()
2052 ratr_mask = 0x000ff015; in rtl92se_update_hal_rate_table()
2054 ratr_mask = 0x000ff005; in rtl92se_update_hal_rate_table()
2057 ratr_mask = 0x0f0ff015; in rtl92se_update_hal_rate_table()
2059 ratr_mask = 0x0f0ff005; in rtl92se_update_hal_rate_table()
2067 ratr_value &= 0x000ff0ff; in rtl92se_update_hal_rate_table()
2069 ratr_value &= 0x0f0ff0ff; in rtl92se_update_hal_rate_table()
2075 ratr_value &= 0x0FFFFFFF; in rtl92se_update_hal_rate_table()
2077 ratr_value &= 0x0FFFFFF0; in rtl92se_update_hal_rate_table()
2083 ratr_value |= 0x10000000; in rtl92se_update_hal_rate_table()
2086 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92se_update_hal_rate_table()
2098 if (ratr_value & 0xfffff000) in rtl92se_update_hal_rate_table()
2117 u8 ratr_index = 0; in rtl92se_update_hal_rate_mask()
2118 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; in rtl92se_update_hal_rate_mask()
2120 1 : 0; in rtl92se_update_hal_rate_mask()
2122 1 : 0; in rtl92se_update_hal_rate_mask()
2123 enum wireless_mode wirelessmode = 0; in rtl92se_update_hal_rate_mask()
2125 u32 ratr_value = 0; in rtl92se_update_hal_rate_mask()
2126 u8 shortgi_rate = 0; in rtl92se_update_hal_rate_mask()
2127 u32 mask = 0; in rtl92se_update_hal_rate_mask()
2128 u32 band = 0; in rtl92se_update_hal_rate_mask()
2130 u8 macid = 0; in rtl92se_update_hal_rate_mask()
2144 ratr_bitmap = sta->supp_rates[0]; in rtl92se_update_hal_rate_mask()
2146 ratr_bitmap = 0xfff; in rtl92se_update_hal_rate_mask()
2148 sta->ht_cap.mcs.rx_mask[0] << 12); in rtl92se_update_hal_rate_mask()
2153 if (ratr_bitmap & 0x0000000c) in rtl92se_update_hal_rate_mask()
2154 ratr_bitmap &= 0x0000000d; in rtl92se_update_hal_rate_mask()
2156 ratr_bitmap &= 0x0000000f; in rtl92se_update_hal_rate_mask()
2163 ratr_bitmap &= 0x00000f00; in rtl92se_update_hal_rate_mask()
2165 ratr_bitmap &= 0x00000ff0; in rtl92se_update_hal_rate_mask()
2167 ratr_bitmap &= 0x00000ff5; in rtl92se_update_hal_rate_mask()
2172 ratr_bitmap &= 0x00000ff0; in rtl92se_update_hal_rate_mask()
2181 ratr_bitmap &= 0x00070000; in rtl92se_update_hal_rate_mask()
2183 ratr_bitmap &= 0x0007f000; in rtl92se_update_hal_rate_mask()
2185 ratr_bitmap &= 0x0007f005; in rtl92se_update_hal_rate_mask()
2190 ratr_bitmap &= 0x000f0000; in rtl92se_update_hal_rate_mask()
2192 ratr_bitmap &= 0x000fc000; in rtl92se_update_hal_rate_mask()
2194 ratr_bitmap &= 0x000ff000; in rtl92se_update_hal_rate_mask()
2197 ratr_bitmap &= 0x000ff015; in rtl92se_update_hal_rate_mask()
2199 ratr_bitmap &= 0x000ff005; in rtl92se_update_hal_rate_mask()
2203 ratr_bitmap &= 0x0f8f0000; in rtl92se_update_hal_rate_mask()
2205 ratr_bitmap &= 0x0f8fc000; in rtl92se_update_hal_rate_mask()
2207 ratr_bitmap &= 0x0f8ff000; in rtl92se_update_hal_rate_mask()
2210 ratr_bitmap &= 0x0f8ff015; in rtl92se_update_hal_rate_mask()
2212 ratr_bitmap &= 0x0f8ff005; in rtl92se_update_hal_rate_mask()
2219 if (macid == 0) in rtl92se_update_hal_rate_mask()
2230 ratr_bitmap &= 0x000ff0ff; in rtl92se_update_hal_rate_mask()
2232 ratr_bitmap &= 0x0f8ff0ff; in rtl92se_update_hal_rate_mask()
2238 ratr_bitmap &= 0x0FFFFFFF; in rtl92se_update_hal_rate_mask()
2240 ratr_bitmap &= 0x0FFFFFF0; in rtl92se_update_hal_rate_mask()
2243 ratr_bitmap |= 0x10000000; in rtl92se_update_hal_rate_mask()
2246 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92se_update_hal_rate_mask()
2256 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf); in rtl92se_update_hal_rate_mask()
2260 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap); in rtl92se_update_hal_rate_mask()
2263 if (macid != 0) in rtl92se_update_hal_rate_mask()
2286 sifs_timer = 0x0e0e; in rtl92se_update_channel_access_setting()
2300 unsigned long flag = 0; in rtl92se_gpio_radio_on_off_checking()
2388 u32 entry_id = 0; in rtl92se_set_key()
2392 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, in rtl92se_set_key()
2393 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, in rtl92se_set_key()
2394 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, in rtl92se_set_key()
2395 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} in rtl92se_set_key()
2398 0xff, 0xff, 0xff, 0xff, 0xff, 0xff in rtl92se_set_key()
2402 u8 idx = 0; in rtl92se_set_key()
2403 u8 cam_offset = 0; in rtl92se_set_key()
2408 for (idx = 0; idx < clear_number; idx++) { in rtl92se_set_key()
2413 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92se_set_key()
2415 rtlpriv->sec.key_len[idx] = 0; in rtl92se_set_key()
2464 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92se_set_key()
2517 pci_read_config_dword(rtlpci->pdev, 0x40, &val); in rtl92se_resume()
2518 if ((val & 0x0000ff00) != 0) in rtl92se_resume()
2519 pci_write_config_dword(rtlpci->pdev, 0x40, in rtl92se_resume()
2520 val & 0xffff00ff); in rtl92se_resume()