Lines Matching +full:0 +full:x88000
29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
78 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
88 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
93 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 0x32c9a
99 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
179 u8 dbi_direct = 0; in rtl92d_phy_query_bb_reg()
195 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92d_phy_query_bb_reg()
205 u8 dbi_direct = 0; in rtl92d_phy_set_bb_reg()
245 u8 rfpi_enable = 0; in _rtl92d_phy_rf_serial_read()
277 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", in _rtl92d_phy_rf_serial_read()
294 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92d_phy_rf_serial_write()
296 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92d_phy_rf_serial_write()
330 if (bitmask == 0) in rtl92d_phy_set_rf_reg()
360 for (i = 0; i < arraylength; i = i + 2) in rtl92d_phy_mac_config()
364 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ in rtl92d_phy_mac_config()
367 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); in rtl92d_phy_mac_config()
370 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); in rtl92d_phy_mac_config()
381 /* 16 LSBs if read 32-bit from 0x870 */ in _rtl92d_phy_init_bb_rf_register_definition()
383 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ in _rtl92d_phy_init_bb_rf_register_definition()
385 /* 16 LSBs if read 32-bit from 0x874 */ in _rtl92d_phy_init_bb_rf_register_definition()
387 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ in _rtl92d_phy_init_bb_rf_register_definition()
391 /* 16 LSBs if read 32-bit from 0x8E0 */ in _rtl92d_phy_init_bb_rf_register_definition()
393 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ in _rtl92d_phy_init_bb_rf_register_definition()
395 /* 16 LSBs if read 32-bit from 0x8E4 */ in _rtl92d_phy_init_bb_rf_register_definition()
397 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ in _rtl92d_phy_init_bb_rf_register_definition()
401 /* 16 LSBs if read 32-bit from 0x860 */ in _rtl92d_phy_init_bb_rf_register_definition()
403 /* 16 LSBs if read 32-bit from 0x864 */ in _rtl92d_phy_init_bb_rf_register_definition()
407 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ in _rtl92d_phy_init_bb_rf_register_definition()
409 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ in _rtl92d_phy_init_bb_rf_register_definition()
509 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; in _rtl92d_phy_config_bb_with_headerfile()
514 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
538 for (i = 0; i < phy_reg_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
544 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", in _rtl92d_phy_config_bb_with_headerfile()
549 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
550 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
558 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
566 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
574 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
581 for (i = 0; i < agctab_5garraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
590 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
611 index = 0; in _rtl92d_store_pwrindex_diffrate_offset()
616 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) in _rtl92d_store_pwrindex_diffrate_offset()
632 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) in _rtl92d_store_pwrindex_diffrate_offset()
647 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", in _rtl92d_store_pwrindex_diffrate_offset()
665 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { in _rtl92d_phy_config_bb_with_pgheaderfile()
700 rtlphy->pwrgroup_cnt = 0; in _rtl92d_phy_bb_config()
715 RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl92d_phy_bb_config()
730 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92d_phy_bb_config()
731 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); in rtl92d_phy_bb_config()
732 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); in rtl92d_phy_bb_config()
733 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ in rtl92d_phy_bb_config()
739 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92d_phy_bb_config()
767 if (rtlpriv->efuse.internal_pa_5g[0]) { in rtl92d_phy_config_rf_with_headerfile()
782 * mac1 start on 5G, mac 0 has to set phy0&phy1 in rtl92d_phy_config_rf_with_headerfile()
792 for (i = 0; i < radioa_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
799 for (i = 0; i < radiob_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
818 rtlphy->default_initialgain[0] = in rtl92d_phy_get_hw_reg_originalvalue()
827 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92d_phy_get_hw_reg_originalvalue()
828 rtlphy->default_initialgain[0], in rtl92d_phy_get_hw_reg_originalvalue()
837 "Default framesync (0x%x) = 0x%x\n", in rtl92d_phy_get_hw_reg_originalvalue()
859 cckpowerlevel[RF90_PATH_A] = 0; in _rtl92d_get_txpower_index()
860 cckpowerlevel[RF90_PATH_B] = 0; in _rtl92d_get_txpower_index()
884 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92d_ccxpower_index_check()
885 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92d_ccxpower_index_check()
912 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], in rtl92d_phy_set_txpower_level()
913 &ofdmpowerlevel[0]); in rtl92d_phy_set_txpower_level()
915 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], in rtl92d_phy_set_txpower_level()
916 &ofdmpowerlevel[0]); in rtl92d_phy_set_txpower_level()
918 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl92d_phy_set_txpower_level()
919 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); in rtl92d_phy_set_txpower_level()
929 unsigned long flag = 0; in rtl92d_phy_set_bw_mode()
955 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl92d_phy_set_bw_mode()
966 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
967 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
973 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
974 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
983 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
986 BIT(11), 0); in rtl92d_phy_set_bw_mode()
987 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
1004 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1005 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1006 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
1007 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
1039 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
1040 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
1045 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_switch_wirelessband()
1048 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
1051 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
1054 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
1057 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
1070 unsigned long flag = 0; in _rtl92d_phy_reload_imr_setting()
1075 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1076 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1077 /* fc area 0xd2c */ in _rtl92d_phy_reload_imr_setting()
1084 /* leave 0 for channel1-14. */ in _rtl92d_phy_reload_imr_setting()
1087 for (i = 0; i < imr_num; i++) in _rtl92d_phy_reload_imr_setting()
1090 rf_imr_param_normal[0][group][i]); in _rtl92d_phy_reload_imr_setting()
1091 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1104 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1106 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1108 for (i = 0; i < imr_num; i++) { in _rtl92d_phy_reload_imr_setting()
1112 rf_imr_param_normal[0][0][i]); in _rtl92d_phy_reload_imr_setting()
1115 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1144 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); in _rtl92d_phy_enable_rf_env()
1147 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in _rtl92d_phy_enable_rf_env()
1151 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1153 /*Set 0 to 12 bits for 8255 */ in _rtl92d_phy_enable_rf_env()
1154 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1189 u8 index = 0, i = 0, rfpath = RF90_PATH_A; in _rtl92d_phy_switch_rf_setting()
1191 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; in _rtl92d_phy_switch_rf_setting()
1199 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
1200 for (i = 0; i < RF_CHNL_NUM_5G; i++) { in _rtl92d_phy_switch_rf_setting()
1202 index = 0; in _rtl92d_phy_switch_rf_setting()
1204 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { in _rtl92d_phy_switch_rf_setting()
1225 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { in _rtl92d_phy_switch_rf_setting()
1226 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { in _rtl92d_phy_switch_rf_setting()
1229 RFREG_OFFSET_MASK, 0xE439D); in _rtl92d_phy_switch_rf_setting()
1232 0x7FF) | (u4tmp << 11); in _rtl92d_phy_switch_rf_setting()
1245 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
1258 value = 0x07; in _rtl92d_phy_switch_rf_setting()
1260 value = 0x02; in _rtl92d_phy_switch_rf_setting()
1262 index = 0; in _rtl92d_phy_switch_rf_setting()
1276 for (i = 0; in _rtl92d_phy_switch_rf_setting()
1284 "offset 0x%x value 0x%x path %d index %d\n", in _rtl92d_phy_switch_rf_setting()
1290 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in _rtl92d_phy_switch_rf_setting()
1298 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
1301 index = 0; in _rtl92d_phy_switch_rf_setting()
1308 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_switch_rf_setting()
1318 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { in _rtl92d_phy_switch_rf_setting()
1332 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
1341 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_switch_rf_setting()
1374 return 0; in rtl92d_get_rightchnlplace_for_iqk()
1387 u8 result = 0; in _rtl92d_phy_patha_iqk()
1392 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_patha_iqk()
1393 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1394 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1396 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1397 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1399 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1400 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1403 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1404 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1405 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1406 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1410 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1413 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1414 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1421 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
1422 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk()
1423 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
1424 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk()
1425 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
1426 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk()
1427 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
1428 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk()
1429 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_patha_iqk()
1430 (((rege9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_patha_iqk()
1431 result |= 0x01; in _rtl92d_phy_patha_iqk()
1435 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_patha_iqk()
1436 (((regeac & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_patha_iqk()
1437 result |= 0x02; in _rtl92d_phy_patha_iqk()
1451 u8 result = 0; in _rtl92d_phy_patha_iqk_5g_normal()
1463 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1464 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1465 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1466 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1469 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1470 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1471 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1472 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1476 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1478 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1479 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1480 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_patha_iqk_5g_normal()
1484 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1485 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1492 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1493 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk_5g_normal()
1494 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1495 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk_5g_normal()
1496 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1497 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk_5g_normal()
1498 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1499 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk_5g_normal()
1501 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { in _rtl92d_phy_patha_iqk_5g_normal()
1502 result |= 0x01; in _rtl92d_phy_patha_iqk_5g_normal()
1511 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_patha_iqk_5g_normal()
1512 result |= 0x02; in _rtl92d_phy_patha_iqk_5g_normal()
1521 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_patha_iqk_5g_normal()
1532 u8 result = 0; in _rtl92d_phy_pathb_iqk()
1537 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1538 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1544 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1545 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk()
1546 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1547 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk()
1548 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1549 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk()
1550 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1551 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk()
1552 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1553 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk()
1554 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_pathb_iqk()
1555 (((regebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_pathb_iqk()
1556 result |= 0x01; in _rtl92d_phy_pathb_iqk()
1559 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_pathb_iqk()
1560 (((regecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_pathb_iqk()
1561 result |= 0x02; in _rtl92d_phy_pathb_iqk()
1573 u8 result = 0; in _rtl92d_phy_pathb_iqk_5g_normal()
1580 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1581 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1582 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1583 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1586 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1587 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1588 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1589 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1593 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1596 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1597 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1599 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_pathb_iqk_5g_normal()
1603 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1604 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1612 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1613 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk_5g_normal()
1614 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1615 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk_5g_normal()
1616 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1617 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk_5g_normal()
1618 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1619 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk_5g_normal()
1620 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1621 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk_5g_normal()
1623 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) in _rtl92d_phy_pathb_iqk_5g_normal()
1624 result |= 0x01; in _rtl92d_phy_pathb_iqk_5g_normal()
1628 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_pathb_iqk_5g_normal()
1629 result |= 0x02; in _rtl92d_phy_pathb_iqk_5g_normal()
1639 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_pathb_iqk_5g_normal()
1653 for (i = 0; i < regnum; i++) in _rtl92d_phy_save_adda_registers()
1664 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_save_mac_registers()
1678 for (i = 0; i < regnum; i++) in _rtl92d_phy_reload_adda_registers()
1689 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_reload_mac_registers()
1702 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl92d_phy_path_adda_on()
1704 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? in _rtl92d_phy_path_adda_on()
1705 0x04db25a4 : 0x0b1b25a4; in _rtl92d_phy_path_adda_on()
1706 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in _rtl92d_phy_path_adda_on()
1717 rtl_write_byte(rtlpriv, macreg[0], 0x3F); in _rtl92d_phy_mac_setting_calibration()
1730 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1731 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1732 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1742 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl92d_phy_pimode_switch()
1743 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1744 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1755 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate()
1756 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate()
1757 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate()
1758 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate()
1761 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate()
1774 if (t == 0) { in _rtl92d_phy_iq_calibrate()
1776 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate()
1789 if (t == 0) in _rtl92d_phy_iq_calibrate()
1797 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1798 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1799 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1800 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1801 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1804 0x00010000); in _rtl92d_phy_iq_calibrate()
1806 0x00010000); in _rtl92d_phy_iq_calibrate()
1812 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1814 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1817 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1818 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1819 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1820 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1822 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1825 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1826 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1827 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1828 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1829 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1830 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1831 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1832 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1834 } else if (i == (retrycount - 1) && patha_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1839 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1840 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1841 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1842 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1845 if (0x00 == patha_ok) in _rtl92d_phy_iq_calibrate()
1851 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1853 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1856 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1857 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1858 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1859 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1860 result[t][6] = (rtl_get_bbreg(hw, 0xec4, in _rtl92d_phy_iq_calibrate()
1861 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1862 result[t][7] = (rtl_get_bbreg(hw, 0xecc, in _rtl92d_phy_iq_calibrate()
1863 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1865 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1869 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1870 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1871 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1872 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1875 if (0x00 == pathb_ok) in _rtl92d_phy_iq_calibrate()
1884 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1885 if (t != 0) { in _rtl92d_phy_iq_calibrate()
1903 /* load 0xe30 IQC default value */ in _rtl92d_phy_iq_calibrate()
1904 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1905 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1918 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate_5g_normal()
1919 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate_5g_normal()
1920 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate_5g_normal()
1921 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate_5g_normal()
1924 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate_5g_normal()
1941 if (t == 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
1943 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate_5g_normal()
1965 if (t == 0) in _rtl92d_phy_iq_calibrate_5g_normal()
1971 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
1972 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1973 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1974 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1975 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
1978 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1980 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1983 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1984 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1985 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1987 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
1989 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1990 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1991 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1992 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1993 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1994 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1995 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1996 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1997 } else if (patha_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
2001 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2002 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2003 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2004 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2013 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
2016 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2017 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2018 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2019 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2020 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2021 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2022 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2023 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2024 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
2027 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2028 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2029 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2030 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2040 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2041 if (t != 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
2070 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ in _rtl92d_phy_simularity_compare()
2078 sim_bitmap = 0; in _rtl92d_phy_simularity_compare()
2079 for (i = 0; i < bound; i++) { in _rtl92d_phy_simularity_compare()
2084 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92d_phy_simularity_compare()
2086 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92d_phy_simularity_compare()
2095 if (sim_bitmap == 0) { in _rtl92d_phy_simularity_compare()
2096 for (i = 0; i < (bound / 4); i++) { in _rtl92d_phy_simularity_compare()
2097 if (final_candidate[i] != 0xFF) { in _rtl92d_phy_simularity_compare()
2106 if (!(sim_bitmap & 0x0F)) { /* path A OK */ in _rtl92d_phy_simularity_compare()
2107 for (i = 0; i < 4; i++) in _rtl92d_phy_simularity_compare()
2109 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ in _rtl92d_phy_simularity_compare()
2110 for (i = 0; i < 2; i++) in _rtl92d_phy_simularity_compare()
2113 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ in _rtl92d_phy_simularity_compare()
2116 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ in _rtl92d_phy_simularity_compare()
2136 if (final_candidate == 0xFF) { in _rtl92d_phy_patha_fill_iqk_matrix()
2140 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
2141 val_x = result[final_candidate][0]; in _rtl92d_phy_patha_fill_iqk_matrix()
2142 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
2143 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
2146 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2148 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
2150 ((val_x * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
2152 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
2153 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
2160 "Y = 0x%lx, tx0_c = 0x%lx\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2162 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
2163 ((tx0_c & 0x3C0) >> 6)); in _rtl92d_phy_patha_fill_iqk_matrix()
2164 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
2165 (tx0_c & 0x3F)); in _rtl92d_phy_patha_fill_iqk_matrix()
2168 ((val_y * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
2169 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2177 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2178 reg = result[final_candidate][3] & 0x3F; in _rtl92d_phy_patha_fill_iqk_matrix()
2179 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2180 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92d_phy_patha_fill_iqk_matrix()
2181 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2195 if (final_candidate == 0xFF) { in _rtl92d_phy_pathb_fill_iqk_matrix()
2199 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2201 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
2202 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
2204 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
2206 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
2208 ((val_x * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2210 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
2211 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
2215 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
2217 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2218 ((tx1_c & 0x3C0) >> 6)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2219 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2220 (tx1_c & 0x3F)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2222 ((val_y * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2226 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2227 reg = result[final_candidate][7] & 0x3F; in _rtl92d_phy_pathb_fill_iqk_matrix()
2228 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2229 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2230 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2243 long regebc, regec4, regecc, regtmp = 0; in rtl92d_phy_iq_calibrate()
2245 unsigned long flag = 0; in rtl92d_phy_iq_calibrate()
2249 for (i = 0; i < 8; i++) { in rtl92d_phy_iq_calibrate()
2250 result[0][i] = 0; in rtl92d_phy_iq_calibrate()
2251 result[1][i] = 0; in rtl92d_phy_iq_calibrate()
2252 result[2][i] = 0; in rtl92d_phy_iq_calibrate()
2253 result[3][i] = 0; in rtl92d_phy_iq_calibrate()
2255 final_candidate = 0xff; in rtl92d_phy_iq_calibrate()
2264 for (i = 0; i < 3; i++) { in rtl92d_phy_iq_calibrate()
2275 0, 1); in rtl92d_phy_iq_calibrate()
2277 final_candidate = 0; in rtl92d_phy_iq_calibrate()
2283 0, 2); in rtl92d_phy_iq_calibrate()
2285 final_candidate = 0; in rtl92d_phy_iq_calibrate()
2293 for (i = 0; i < 8; i++) in rtl92d_phy_iq_calibrate()
2296 if (regtmp != 0) in rtl92d_phy_iq_calibrate()
2299 final_candidate = 0xFF; in rtl92d_phy_iq_calibrate()
2304 for (i = 0; i < 4; i++) { in rtl92d_phy_iq_calibrate()
2305 rege94 = result[i][0]; in rtl92d_phy_iq_calibrate()
2318 if (final_candidate != 0xff) { in rtl92d_phy_iq_calibrate()
2319 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; in rtl92d_phy_iq_calibrate()
2335 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ in rtl92d_phy_iq_calibrate()
2336 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ in rtl92d_phy_iq_calibrate()
2338 if ((rege94 != 0) /*&&(regea4 != 0) */) in rtl92d_phy_iq_calibrate()
2340 final_candidate, (regea4 == 0)); in rtl92d_phy_iq_calibrate()
2342 if ((regeb4 != 0) /*&&(regec4 != 0) */) in rtl92d_phy_iq_calibrate()
2344 final_candidate, (regec4 == 0)); in rtl92d_phy_iq_calibrate()
2346 if (final_candidate != 0xFF) { in rtl92d_phy_iq_calibrate()
2350 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl92d_phy_iq_calibrate()
2352 value[0][i] = result[final_candidate][i]; in rtl92d_phy_iq_calibrate()
2374 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && in rtl92d_phy_reload_iqk_setting()
2384 indexforchannel == 0) || indexforchannel > 0) { in rtl92d_phy_reload_iqk_setting()
2389 value[0] != NULL) in rtl92d_phy_reload_iqk_setting()
2390 /*&&(regea4 != 0) */) in rtl92d_phy_reload_iqk_setting()
2393 indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
2395 indexforchannel].value[0][2] == 0)); in rtl92d_phy_reload_iqk_setting()
2398 indexforchannel].value[0][4] != 0) in rtl92d_phy_reload_iqk_setting()
2399 /*&&(regec4 != 0) */) in rtl92d_phy_reload_iqk_setting()
2403 indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
2405 indexforchannel].value[0][6] in rtl92d_phy_reload_iqk_setting()
2406 == 0)); in rtl92d_phy_reload_iqk_setting()
2430 for (i = 0; i < sizeof(channel5g); i++) in _rtl92d_is_legal_5g_channel()
2441 u32 smallest_abs_val = 0xffffffff, u4tmp; in _rtl92d_phy_calc_curvindex()
2445 for (i = 0; i < chnl_num; i++) { in _rtl92d_phy_calc_curvindex()
2448 curveindex[i] = 0; in _rtl92d_phy_calc_curvindex()
2449 for (j = 0; j < (CV_CURVE_CNT * 2); j++) { in _rtl92d_phy_calc_curvindex()
2458 smallest_abs_val = 0xffffffff; in _rtl92d_phy_calc_curvindex()
2472 u32 u4tmp = 0, u4regvalue = 0; in _rtl92d_phy_reload_lck_setting()
2482 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
2493 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
2501 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
2503 rtlpriv->rtlhal.interfaceindex == 0) { in _rtl92d_phy_reload_lck_setting()
2511 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
2513 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_reload_lck_setting()
2514 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); in _rtl92d_phy_reload_lck_setting()
2532 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; in _rtl92d_phy_lc_calibrate_sw()
2533 u16 timeout = 800, timecount = 0; in _rtl92d_phy_lc_calibrate_sw()
2536 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl92d_phy_lc_calibrate_sw()
2539 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2540 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92d_phy_lc_calibrate_sw()
2542 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_lc_calibrate_sw()
2543 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
2544 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2546 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2550 RFREG_OFFSET_MASK, 0x010000); in _rtl92d_phy_lc_calibrate_sw()
2554 BIT(17), 0x0); in _rtl92d_phy_lc_calibrate_sw()
2557 0x08000, 0x01); in _rtl92d_phy_lc_calibrate_sw()
2570 if (index == 0 && rtlhal->interfaceindex == 0) { in _rtl92d_phy_lc_calibrate_sw()
2577 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2); in _rtl92d_phy_lc_calibrate_sw()
2580 0x08000, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2581 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); in _rtl92d_phy_lc_calibrate_sw()
2583 for (i = 0; i < CV_CURVE_CNT; i++) { in _rtl92d_phy_lc_calibrate_sw()
2584 u32 readval = 0, readval2 = 0; in _rtl92d_phy_lc_calibrate_sw()
2585 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, in _rtl92d_phy_lc_calibrate_sw()
2586 0x7f, i); in _rtl92d_phy_lc_calibrate_sw()
2588 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, in _rtl92d_phy_lc_calibrate_sw()
2589 RFREG_OFFSET_MASK, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2591 0x4F, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2592 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; in _rtl92d_phy_lc_calibrate_sw()
2593 /* reg 0x4f [4:0] */ in _rtl92d_phy_lc_calibrate_sw()
2594 /* reg 0x50 [19:10] */ in _rtl92d_phy_lc_calibrate_sw()
2596 0x50, 0xffc00); in _rtl92d_phy_lc_calibrate_sw()
2597 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | in _rtl92d_phy_lc_calibrate_sw()
2600 if (index == 0 && rtlhal->interfaceindex == 0) in _rtl92d_phy_lc_calibrate_sw()
2610 BIT(17), 0x1); in _rtl92d_phy_lc_calibrate_sw()
2614 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2615 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2616 rtl_write_byte(rtlpriv, offset, 0x50); in _rtl92d_phy_lc_calibrate_sw()
2619 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2620 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92d_phy_lc_calibrate_sw()
2622 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2623 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2640 u32 timeout = 2000, timecount = 0; in rtl92d_phy_lc_calibrate()
2698 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ in rtl92d_phy_reset_iqk_result()
2699 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { in rtl92d_phy_reset_iqk_result()
2700 rtlphy->iqk_matrix[i].value[0][0] = 0x100; in rtl92d_phy_reset_iqk_result()
2701 rtlphy->iqk_matrix[i].value[0][2] = 0x100; in rtl92d_phy_reset_iqk_result()
2702 rtlphy->iqk_matrix[i].value[0][4] = 0x100; in rtl92d_phy_reset_iqk_result()
2703 rtlphy->iqk_matrix[i].value[0][6] = 0x100; in rtl92d_phy_reset_iqk_result()
2704 rtlphy->iqk_matrix[i].value[0][1] = 0x0; in rtl92d_phy_reset_iqk_result()
2705 rtlphy->iqk_matrix[i].value[0][3] = 0x0; in rtl92d_phy_reset_iqk_result()
2706 rtlphy->iqk_matrix[i].value[0][5] = 0x0; in rtl92d_phy_reset_iqk_result()
2707 rtlphy->iqk_matrix[i].value[0][7] = 0x0; in rtl92d_phy_reset_iqk_result()
2728 precommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2731 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2733 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2734 postcommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2736 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2737 rfdependcmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2740 RF_CHNLBW, channel, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2743 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2747 case 0: in _rtl92d_phy_sw_chnl_step_by_step()
2762 (*step) = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2783 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92d_phy_sw_chnl_step_by_step()
2786 0xffffff00) | currentcmd->para2); in _rtl92d_phy_sw_chnl_step_by_step()
2832 u32 timeout = 1000, timecount = 0; in rtl92d_phy_sw_chnl()
2837 return 0; in rtl92d_phy_sw_chnl()
2839 return 0; in rtl92d_phy_sw_chnl()
2844 return 0; in rtl92d_phy_sw_chnl()
2854 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2856 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2864 return 0; in rtl92d_phy_sw_chnl()
2871 return 0; in rtl92d_phy_sw_chnl()
2880 if (channel == 0) in rtl92d_phy_sw_chnl()
2882 rtlphy->sw_chnl_stage = 0; in rtl92d_phy_sw_chnl()
2883 rtlphy->sw_chnl_step = 0; in rtl92d_phy_sw_chnl()
2893 if (delay > 0) in rtl92d_phy_sw_chnl()
2924 de_digtable->cur_igvalue = 0x37; in rtl92d_phy_set_io()
2979 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ in _rtl92d_phy_set_rfon()
2980 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ in _rtl92d_phy_set_rfon()
2982 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92d_phy_set_rfon()
2983 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ in _rtl92d_phy_set_rfon()
2984 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2986 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ in _rtl92d_phy_set_rfon()
2987 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfon()
2988 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ in _rtl92d_phy_set_rfon()
2989 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ in _rtl92d_phy_set_rfon()
2990 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfon()
2991 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2992 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ in _rtl92d_phy_set_rfon()
2993 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfon()
3002 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in _rtl92d_phy_set_rfsleep()
3003 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_set_rfsleep()
3004 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ in _rtl92d_phy_set_rfsleep()
3005 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3006 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ in _rtl92d_phy_set_rfsleep()
3007 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3008 /* d. APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
3009 * APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
3010 * RF path 0 offset 0x00 = 0x00 in _rtl92d_phy_set_rfsleep()
3011 * APSD_CTRL 0x600[7:0] = 0x40 in _rtl92d_phy_set_rfsleep()
3013 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3014 while (u4btmp != 0 && delay > 0) { in _rtl92d_phy_set_rfsleep()
3015 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92d_phy_set_rfsleep()
3016 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3017 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3018 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3021 if (delay == 0) { in _rtl92d_phy_set_rfsleep()
3023 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfsleep()
3025 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3026 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfsleep()
3027 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfsleep()
3032 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ in _rtl92d_phy_set_rfsleep()
3033 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3034 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ in _rtl92d_phy_set_rfsleep()
3036 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92d_phy_set_rfsleep()
3037 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ in _rtl92d_phy_set_rfsleep()
3060 u32 initializecount = 0; in rtl92d_phy_set_rf_power_state()
3106 for (queue_id = 0, i = 0; in rtl92d_phy_set_rf_power_state()
3109 if (skb_queue_len(&ring->queue) == 0 || in rtl92d_phy_set_rf_power_state()
3115 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", in rtl92d_phy_set_rf_power_state()
3167 rtl_write_byte(rtlpriv, offset, 0xF3); in rtl92d_phy_config_macphymode()
3172 rtl_write_byte(rtlpriv, offset, 0xF4); in rtl92d_phy_config_macphymode()
3177 rtl_write_byte(rtlpriv, offset, 0xF1); in rtl92d_phy_config_macphymode()
3207 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_config_macphymode_info()
3234 group = 0; in rtl92d_get_chnlgroup_fromarray()
3267 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); in rtl92d_phy_set_poweron()
3269 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_set_poweron()
3285 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_set_poweron()
3294 for (i = 0; i < 200; i++) { in rtl92d_phy_set_poweron()
3295 if ((value8 & BIT(7)) == 0) { in rtl92d_phy_set_poweron()
3317 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3318 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3319 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); in rtl92d_phy_config_maccoexist_rfpage()
3322 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); in rtl92d_phy_config_maccoexist_rfpage()
3323 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3324 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); in rtl92d_phy_config_maccoexist_rfpage()
3327 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3328 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); in rtl92d_phy_config_maccoexist_rfpage()
3329 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); in rtl92d_phy_config_maccoexist_rfpage()
3345 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ in rtl92d_update_bbrf_configuration()
3347 /* r_select_5G for path_A/B,0x878 */ in rtl92d_update_bbrf_configuration()
3348 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
3349 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
3351 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
3352 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
3354 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ in rtl92d_update_bbrf_configuration()
3355 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
3356 /* fc_area 0xd2c */ in rtl92d_update_bbrf_configuration()
3357 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
3359 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
3360 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
3362 0x40000100); in rtl92d_update_bbrf_configuration()
3364 0x40000100); in rtl92d_update_bbrf_configuration()
3374 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
3375 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
3376 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
3390 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
3391 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
3398 BIT(31) | BIT(15), 0); in rtl92d_update_bbrf_configuration()
3403 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
3404 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
3406 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
3407 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
3409 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ in rtl92d_update_bbrf_configuration()
3410 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
3412 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
3414 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
3415 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
3416 if (rtlefuse->internal_pa_5g[0]) in rtl92d_update_bbrf_configuration()
3418 0x2d4000b5); in rtl92d_update_bbrf_configuration()
3421 0x20000080); in rtl92d_update_bbrf_configuration()
3424 0x2d4000b5); in rtl92d_update_bbrf_configuration()
3427 0x20000080); in rtl92d_update_bbrf_configuration()
3453 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3454 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3455 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3457 BIT(26) | BIT(24), 0x00); in rtl92d_update_bbrf_configuration()
3458 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3459 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3460 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
3466 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
3468 BIT(18), 0); in rtl92d_update_bbrf_configuration()
3470 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in rtl92d_update_bbrf_configuration()
3471 0x1c000, 0x07); in rtl92d_update_bbrf_configuration()
3473 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
3482 /* Use antenna 0,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
3483 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
3484 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
3487 if (rtlhal->interfaceindex == 0) { in rtl92d_update_bbrf_configuration()
3489 BIT(13), 0x3); in rtl92d_update_bbrf_configuration()
3493 "MAC1 use DBI to update 0x888\n"); in rtl92d_update_bbrf_configuration()
3494 /* 0x888 */ in rtl92d_update_bbrf_configuration()
3504 /* Use antenna 0 & 1,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
3505 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
3506 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
3507 /* disable ad/da clock1,0x888 */ in rtl92d_update_bbrf_configuration()
3508 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()
3514 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, in rtl92d_update_bbrf_configuration()
3517 for (i = 0; i < 2; i++) in rtl92d_update_bbrf_configuration()
3518 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", in rtl92d_update_bbrf_configuration()
3537 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_check_poweroff()