Lines Matching +full:0 +full:xa600
34 module_param(ap_mode_default, bool, 0);
39 #define MWL8K_HIU_GEN_PTR 0x00000c10
40 #define MWL8K_MODE_STA 0x0000005a
41 #define MWL8K_MODE_AP 0x000000a5
42 #define MWL8K_HIU_INT_CODE 0x00000c14
43 #define MWL8K_FWSTA_READY 0xf0f1f2f4
44 #define MWL8K_FWAP_READY 0xf1f2f4a5
45 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
46 #define MWL8K_HIU_SCRATCH 0x00000c40
49 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
57 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
60 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
75 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
78 * located at offset 0xA600. This
83 #define MWL8K_HW_TIMER_REGISTER 0x0000a600
84 #define BBU_RXRDY_CNT_REG 0x0000a860
85 #define NOK_CCA_CNT_REG 0x0000a6a0
86 #define BBU_AVG_NOISE_VAL 0x67
405 #define MWL8K_CMD_GET 0x0000
406 #define MWL8K_CMD_SET 0x0001
407 #define MWL8K_CMD_SET_LIST 0x0002
410 #define MWL8K_CMD_CODE_DNLD 0x0001
411 #define MWL8K_CMD_GET_HW_SPEC 0x0003
412 #define MWL8K_CMD_SET_HW_SPEC 0x0004
413 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
414 #define MWL8K_CMD_GET_STAT 0x0014
415 #define MWL8K_CMD_BBP_REG_ACCESS 0x001a
416 #define MWL8K_CMD_RADIO_CONTROL 0x001c
417 #define MWL8K_CMD_RF_TX_POWER 0x001e
418 #define MWL8K_CMD_TX_POWER 0x001f
419 #define MWL8K_CMD_RF_ANTENNA 0x0020
420 #define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
421 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
422 #define MWL8K_CMD_SET_POST_SCAN 0x0108
423 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
424 #define MWL8K_CMD_SET_AID 0x010d
425 #define MWL8K_CMD_SET_RATE 0x0110
426 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
427 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
428 #define MWL8K_CMD_SET_SLOT 0x0114
429 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
430 #define MWL8K_CMD_SET_WMM_MODE 0x0123
431 #define MWL8K_CMD_MIMO_CONFIG 0x0125
432 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
433 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
434 #define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
435 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
436 #define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
437 #define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
438 #define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
439 #define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
440 #define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
441 #define MWL8K_CMD_UPDATE_STADB 0x1123
442 #define MWL8K_CMD_BASTREAM 0x1125
454 } while (0) in mwl8k_cmd_name()
455 switch (command & ~0x8000) { in mwl8k_cmd_name()
488 snprintf(buf, bufsize, "0x%x", cmd); in mwl8k_cmd_name()
523 FW_STATE_INIT = 0,
586 return 0; in mwl8k_request_firmware()
613 iowrite32(0, regs + MWL8K_HIU_INT_CODE); in mwl8k_send_fw_load_cmd()
625 if (int_code == 0) in mwl8k_send_fw_load_cmd()
630 iowrite32(0, regs + MWL8K_HIU_INT_CODE); in mwl8k_send_fw_load_cmd()
640 return loops ? 0 : -ETIMEDOUT; in mwl8k_send_fw_load_cmd()
648 int rc = 0; in mwl8k_load_fw_image()
655 cmd->seq_num = 0; in mwl8k_load_fw_image()
656 cmd->macid = 0; in mwl8k_load_fw_image()
657 cmd->result = 0; in mwl8k_load_fw_image()
659 done = 0; in mwl8k_load_fw_image()
676 cmd->length = 0; in mwl8k_load_fw_image()
689 int may_continue, rc = 0; in mwl8k_feed_fw_image()
696 done = 0; in mwl8k_feed_fw_image()
697 prev_block_size = 0; in mwl8k_feed_fw_image()
699 while (may_continue > 0) { in mwl8k_feed_fw_image()
716 if (length == 0) { in mwl8k_feed_fw_image()
717 rc = 0; in mwl8k_feed_fw_image()
721 if (block_size == 0) { in mwl8k_feed_fw_image()
736 if (!rc && length != 0) in mwl8k_feed_fw_image()
801 return loops ? 0 : -ETIMEDOUT; in mwl8k_load_firmware()
861 if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) { in mwl8k_add_dma_header()
882 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); in mwl8k_add_dma_header()
899 int head_pad = 0; in mwl8k_encapsulate_tx_frame()
918 data_pad = 0; in mwl8k_encapsulate_tx_frame()
958 #define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80
959 #define MWL8K_AP_RATE_INFO_40MHZ 0x40
960 #define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
962 #define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80
965 #define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
966 #define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
967 #define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
968 #define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
969 #define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
986 rxd->rx_ctrl = 0; in mwl8k_rxd_ap_refill()
999 memset(status, 0, sizeof(*status)); in mwl8k_rxd_ap_process()
1012 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) { in mwl8k_rxd_ap_process()
1068 #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
1069 #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
1070 #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
1071 #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
1072 #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
1073 #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
1075 #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
1076 #define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
1077 /* ICV=0 or MIC=1 */
1078 #define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1080 #define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
1097 rxd->rx_ctrl = 0; in mwl8k_rxd_sta_refill()
1113 memset(status, 0, sizeof(*status)); in mwl8k_rxd_sta_process()
1166 rxq->rxd_count = 0; in mwl8k_rxq_init()
1167 rxq->head = 0; in mwl8k_rxq_init()
1168 rxq->tail = 0; in mwl8k_rxq_init()
1184 for (i = 0; i < MWL8K_RX_DESCS; i++) { in mwl8k_rxq_init()
1195 nexti = 0; in mwl8k_rxq_init()
1201 return 0; in mwl8k_rxq_init()
1210 refilled = 0; in rxq_refill()
1227 rxq->tail = 0; in rxq_refill()
1250 for (i = 0; i < MWL8K_RX_DESCS; i++) { in mwl8k_rxq_deinit()
1255 dma_unmap_addr_set(&rxq->buf[i], dma, 0); in mwl8k_rxq_deinit()
1310 ETH_ALEN) == 0) in mwl8k_find_vif_bss()
1324 processed = 0; in rxq_process()
1341 if (pkt_len < 0) in rxq_process()
1349 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); in rxq_process()
1353 rxq->head = 0; in rxq_process()
1388 * 0 for triggering Counter in rxq_process()
1394 memset((void *)&(tr->data), 0, 4); in rxq_process()
1421 #define MWL8K_TXD_STATUS_OK 0x00000001
1422 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1423 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1424 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1425 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1427 #define MWL8K_QOS_QLEN_UNSPEC 0xff00
1428 #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1429 #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1430 #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1431 #define MWL8K_QOS_EOSP 0x0010
1457 txq->len = 0; in mwl8k_txq_init()
1458 txq->head = 0; in mwl8k_txq_init()
1459 txq->tail = 0; in mwl8k_txq_init()
1475 for (i = 0; i < MWL8K_TX_DESCS; i++) { in mwl8k_txq_init()
1482 tx_desc->status = 0; in mwl8k_txq_init()
1487 return 0; in mwl8k_txq_init()
1504 for (i = 0; i < mwl8k_tx_queues(priv); i++) { in mwl8k_dump_tx_rings()
1506 int fw_owned = 0; in mwl8k_dump_tx_rings()
1507 int drv_owned = 0; in mwl8k_dump_tx_rings()
1508 int unused = 0; in mwl8k_dump_tx_rings()
1511 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { in mwl8k_dump_tx_rings()
1521 if (tx_desc->pkt_len == 0) in mwl8k_dump_tx_rings()
1555 return 0; in mwl8k_tx_wait_empty()
1561 return 0; in mwl8k_tx_wait_empty()
1568 return 0; in mwl8k_tx_wait_empty()
1571 rc = 0; in mwl8k_tx_wait_empty()
1589 return 0; in mwl8k_tx_wait_empty()
1603 retry = 0; in mwl8k_tx_wait_empty()
1641 case 0: in mwl8k_tid_queue_mapping()
1663 #define RI_FORMAT(a) (a & 0x0001)
1664 #define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
1673 processed = 0; in mwl8k_txq_reclaim()
1674 while (txq->len > 0 && limit--) { in mwl8k_txq_reclaim()
1700 BUG_ON(txq->len == 0); in mwl8k_txq_reclaim()
1717 tx_desc->pkt_phys_addr = 0; in mwl8k_txq_reclaim()
1718 tx_desc->pkt_len = 0; in mwl8k_txq_reclaim()
1731 * legacy station (format = 0), do not form an in mwl8k_txq_reclaim()
1735 RI_FORMAT(rate_info) == 0) { in mwl8k_txq_reclaim()
1749 info->status.rates[0].idx = -1; in mwl8k_txq_reclaim()
1750 info->status.rates[0].count = 1; in mwl8k_txq_reclaim()
1791 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) { in mwl8k_add_stream()
1813 return 0; in mwl8k_start_stream()
1814 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0); in mwl8k_start_stream()
1829 memset(stream, 0, sizeof(*stream)); in mwl8k_remove_stream()
1838 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) { in mwl8k_lookup_stream()
1871 if (tx_stats->start_time == 0) in mwl8k_tx_count_packet()
1879 tx_stats->pkts = 0; in mwl8k_tx_count_packet()
1880 tx_stats->start_time = 0; in mwl8k_tx_count_packet()
1887 * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
1909 u8 tid = 0; in mwl8k_txq_xmit()
1920 qos = 0; in mwl8k_txq_xmit()
1931 mwl8k_add_dma_header(priv, skb, 0, 0); in mwl8k_txq_xmit()
1941 mwl8k_vif->seqno += 0x10; in mwl8k_txq_xmit()
1945 txstatus = 0; in mwl8k_txq_xmit()
1946 txdatarate = 0; in mwl8k_txq_xmit()
1949 txdatarate = 0; in mwl8k_txq_xmit()
1985 tid = qos & 0xf; in mwl8k_txq_xmit()
2012 * after the ADDBA request with SSN 0. This in mwl8k_txq_xmit()
2096 tx->rate_info = 0; in mwl8k_txq_xmit()
2100 tx->peer_id = 0; in mwl8k_txq_xmit()
2106 tx->timestamp = 0; in mwl8k_txq_xmit()
2116 txq->tail = 0; in mwl8k_txq_xmit()
2173 return 0; in mwl8k_fw_lock()
2207 unsigned long timeout = 0; in mwl8k_post_cmd()
2209 u32 bitmap = 0; in mwl8k_post_cmd()
2238 cmd->result = (__force __le16) 0xffff; in mwl8k_post_cmd()
2273 rc = cmd->result ? -EINVAL : 0; in mwl8k_post_cmd()
2275 wiphy_err(hw->wiphy, "Command %s error 0x%x\n", in mwl8k_post_cmd()
2366 #define MWL8K_CAP_MAX_AMSDU 0x20000000
2367 #define MWL8K_CAP_GREENFIELD 0x08000000
2368 #define MWL8K_CAP_AMPDU 0x04000000
2369 #define MWL8K_CAP_RX_STBC 0x01000000
2370 #define MWL8K_CAP_TX_STBC 0x00800000
2371 #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2372 #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2373 #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2374 #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2375 #define MWL8K_CAP_DELAY_BA 0x00003000
2376 #define MWL8K_CAP_MIMO 0x00000200
2377 #define MWL8K_CAP_40MHZ 0x00000100
2378 #define MWL8K_CAP_BAND_MASK 0x00000007
2379 #define MWL8K_CAP_5GHZ 0x00000004
2380 #define MWL8K_CAP_2GHZ4 0x00000001
2416 band->ht_cap.mcs.rx_mask[0] = 0xff; in mwl8k_set_ht_caps()
2418 band->ht_cap.mcs.rx_mask[1] = 0xff; in mwl8k_set_ht_caps()
2420 band->ht_cap.mcs.rx_mask[2] = 0xff; in mwl8k_set_ht_caps()
2421 band->ht_cap.mcs.rx_mask[4] = 0x01; in mwl8k_set_ht_caps()
2468 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); in mwl8k_cmd_get_hw_spec_sta()
2470 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); in mwl8k_cmd_get_hw_spec_sta()
2472 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_cmd_get_hw_spec_sta()
2485 priv->ap_macids_supported = 0x00000000; in mwl8k_cmd_get_hw_spec_sta()
2486 priv->sta_macids_supported = 0x00000001; in mwl8k_cmd_get_hw_spec_sta()
2533 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); in mwl8k_cmd_get_hw_spec_ap()
2556 priv->ap_macids_supported = 0x000000ff; in mwl8k_cmd_get_hw_spec_ap()
2557 priv->sta_macids_supported = 0x00000100; in mwl8k_cmd_get_hw_spec_ap()
2566 off = le32_to_cpu(cmd->rxwrptr) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2567 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off); in mwl8k_cmd_get_hw_spec_ap()
2569 off = le32_to_cpu(cmd->rxrdptr) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2570 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off); in mwl8k_cmd_get_hw_spec_ap()
2572 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2573 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2574 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2575 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2577 for (i = 0; i < priv->num_ampdu_queues; i++) in mwl8k_cmd_get_hw_spec_ap()
2579 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff; in mwl8k_cmd_get_hw_spec_ap()
2615 #define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
2616 #define MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR 0x00000200
2617 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2618 #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2619 #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
2636 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); in mwl8k_cmd_set_hw_spec()
2645 for (i = 0; i < mwl8k_tx_queues(priv); i++) { in mwl8k_cmd_set_hw_spec()
2674 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
2675 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
2676 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2677 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
2686 int mc_count = 0; in __mwl8k_cmd_mac_multicast_adr()
2693 mc_count = 0; in __mwl8k_cmd_mac_multicast_adr()
2711 int i = 0; in __mwl8k_cmd_mac_multicast_adr()
2783 return 0; in mwl8k_cmd_radio_control()
2793 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); in mwl8k_cmd_radio_control()
2806 return mwl8k_cmd_radio_control(hw, 0, 0); in mwl8k_cmd_radio_disable()
2811 return mwl8k_cmd_radio_control(hw, 1, 0); in mwl8k_cmd_radio_enable()
2893 cmd->band = cpu_to_le16(0x1); in mwl8k_cmd_tx_power()
2895 cmd->band = cpu_to_le16(0x4); in mwl8k_cmd_tx_power()
2901 cmd->bw = cpu_to_le16(0x2); in mwl8k_cmd_tx_power()
2903 cmd->bw = cpu_to_le16(0x4); in mwl8k_cmd_tx_power()
2905 cmd->sub_ch = cpu_to_le16(0x3); in mwl8k_cmd_tx_power()
2907 cmd->sub_ch = cpu_to_le16(0x1); in mwl8k_cmd_tx_power()
2910 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++) in mwl8k_cmd_tx_power()
3041 *value = 0; in mwl8k_cmd_bbp_reg_access()
3069 cmd->isibss = 0; in mwl8k_cmd_set_post_scan()
3081 int band, ch, idx = 0; in freq_to_idx()
3088 for (ch = 0; ch < sband->n_channels; ch++, idx++) in freq_to_idx()
3101 s8 nf = 0, idx; in mwl8k_update_survey()
3125 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &nf); in mwl8k_update_survey()
3166 cmd->channel_flags |= cpu_to_le32(0x00000001); in mwl8k_cmd_set_rf_channel()
3168 cmd->channel_flags |= cpu_to_le32(0x00000004); in mwl8k_cmd_set_rf_channel()
3173 cmd->channel_flags |= cpu_to_le32(0x00000080); in mwl8k_cmd_set_rf_channel()
3175 cmd->channel_flags |= cpu_to_le32(0x000001900); in mwl8k_cmd_set_rf_channel()
3177 cmd->channel_flags |= cpu_to_le32(0x000000900); in mwl8k_cmd_set_rf_channel()
3179 cmd->channel_flags |= cpu_to_le32(0x00000080); in mwl8k_cmd_set_rf_channel()
3187 if (priv->channel_time != 0) in mwl8k_cmd_set_rf_channel()
3203 #define MWL8K_FRAME_PROT_DISABLED 0x00
3204 #define MWL8K_FRAME_PROT_11G 0x07
3205 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
3206 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
3226 mask &= 0x1fef; in legacy_rate_mask_to_array()
3228 for (i = 0, j = 0; i < 13; i++) { in legacy_rate_mask_to_array()
3339 if (payload_len < 0) in mwl8k_cmd_finalize_join()
3340 payload_len = 0; in mwl8k_cmd_finalize_join()
3425 /* Log exponent of max contention period: 0...15 */
3428 /* Log exponent of min contention period: 0...15 */
3438 /* Log exponent of max contention period: 0...15 */
3441 /* Log exponent of min contention period: 0...15 */
3453 #define MWL8K_SET_EDCA_CW 0x01
3454 #define MWL8K_SET_EDCA_TXOP 0x02
3455 #define MWL8K_SET_EDCA_AIFS 0x04
3577 #define MWL8K_USE_AUTO_RATE 0x0002
3578 #define MWL8K_UCAST_RATE 0
3679 #define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3816 u8 bitmap = 0, stream_index; in mwl8k_watchdog_ba_events()
3822 u32 status = 0; in mwl8k_watchdog_ba_events()
3833 for (i = 0; i < TOTAL_HW_TX_QUEUES; i++) { in mwl8k_watchdog_ba_events()
3876 return 0; in mwl8k_cmd_bss_start()
3879 return 0; in mwl8k_cmd_bss_start()
3924 #define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3925 #define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3983 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr, in mwl8k_check_ba()
4021 cmd->create_params.curr_seq_no = cpu_to_le16(0); in mwl8k_create_ba()
4089 #define MWL8K_STA_ACTION_ADD 0
4116 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0]; in mwl8k_cmd_set_new_stn_add()
4162 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) { in mwl8k_cmd_set_new_stn_del()
4166 if (memcmp(s->sta->addr, addr, ETH_ALEN) == 0) { in mwl8k_cmd_set_new_stn_del()
4240 #define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
4252 #define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
4253 #define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
4254 #define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
4255 #define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
4256 #define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
4298 if (key->keyidx == 0) in mwl8k_encryption_set_cmd_info()
4320 return 0; in mwl8k_encryption_set_cmd_info()
4340 if (rc < 0) in mwl8k_cmd_encryption_set_key()
4397 if (rc < 0) in mwl8k_cmd_encryption_remove_key()
4402 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0; in mwl8k_cmd_encryption_remove_key()
4419 int rc = 0; in mwl8k_set_key()
4552 p->amsdu_enabled = 0; in mwl8k_cmd_update_stadb_add()
4644 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_tx_poll()
4645 limit -= mwl8k_txq_reclaim(hw, i, limit, 0); in mwl8k_tx_poll()
4669 limit -= rxq_process(hw, 0, limit); in mwl8k_rx_poll()
4670 limit -= rxq_refill(hw, 0, limit); in mwl8k_rx_poll()
4730 rc = mwl8k_cmd_enable_sniffer(hw, 0); in mwl8k_start()
4741 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); in mwl8k_start()
4744 rc = mwl8k_cmd_set_wmm_mode(hw, 0); in mwl8k_start()
4750 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); in mwl8k_start()
4773 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); in mwl8k_stop()
4790 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_stop()
4856 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); in mwl8k_add_interface()
4859 mwl8k_vif->seqno = 0; in mwl8k_add_interface()
4872 return 0; in mwl8k_add_interface()
4985 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); in mwl8k_config()
4999 u32 ap_legacy_rates = 0; in mwl8k_bss_info_changed_sta()
5179 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list); in mwl8k_prepare_multicast()
5200 return 0; in mwl8k_configure_filter_sniffer()
5205 return 0; in mwl8k_configure_filter_sniffer()
5261 mwl8k_cmd_enable_sniffer(hw, 0); in mwl8k_configure_filter()
5341 if (ret >= 0) { in mwl8k_sta_add()
5345 ret = 0; in mwl8k_sta_add()
5352 for (i = 0; i < NUM_WEP_KEYS; i++) { in mwl8k_sta_add()
5420 return 0; in mwl8k_get_survey()
5423 if (idx != 0) in mwl8k_get_survey()
5430 return 0; in mwl8k_get_survey()
5444 int i, rc = 0; in mwl8k_ampdu_action()
5470 *ssn = 0; in mwl8k_ampdu_action()
5490 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) { in mwl8k_ampdu_action()
5578 priv->channel_time = 0; in mwl8k_sw_scan_start()
5581 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp); in mwl8k_sw_scan_start()
5598 priv->channel_time = 0; in mwl8k_sw_scan_complete()
5601 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp); in mwl8k_sw_scan_complete()
5647 MWL8363 = 0,
5697 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
5698 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5699 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
5700 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5701 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5702 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
5703 { PCI_VDEVICE(MARVELL, 0x2a41), .driver_data = MWL8366, },
5704 { PCI_VDEVICE(MARVELL, 0x2a42), .driver_data = MWL8366, },
5705 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
5706 { PCI_VDEVICE(MARVELL, 0x2b36), .driver_data = MWL8764, },
5723 return 0; in mwl8k_request_alt_fw()
5848 int rc = 0; in mwl8k_init_txqs()
5851 for (i = 0; i < mwl8k_tx_queues(priv); i++) { in mwl8k_init_txqs()
5866 int rc = 0; in mwl8k_probe_hw()
5883 priv->pending_tx_pkts = 0; in mwl8k_probe_hw()
5884 atomic_set(&priv->watchdog_event_pending, 0); in mwl8k_probe_hw()
5886 rc = mwl8k_rxq_init(hw, 0); in mwl8k_probe_hw()
5889 rxq_refill(hw, 0, INT_MAX); in mwl8k_probe_hw()
5897 priv->num_ampdu_queues = 0; in mwl8k_probe_hw()
5904 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); in mwl8k_probe_hw()
5905 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); in mwl8k_probe_hw()
5926 memset(priv->ampdu, 0, sizeof(priv->ampdu)); in mwl8k_probe_hw()
5965 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3); in mwl8k_probe_hw()
5968 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); in mwl8k_probe_hw()
5974 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); in mwl8k_probe_hw()
5981 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, in mwl8k_probe_hw()
5982 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); in mwl8k_probe_hw()
5984 return 0; in mwl8k_probe_hw()
5987 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); in mwl8k_probe_hw()
5991 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_probe_hw()
5993 mwl8k_rxq_deinit(hw, 0); in mwl8k_probe_hw()
6007 int i, rc = 0; in mwl8k_reload_firmware()
6012 mwl8k_rxq_deinit(hw, 0); in mwl8k_reload_firmware()
6023 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_reload_firmware()
6041 rc = mwl8k_config(hw, ~0); in mwl8k_reload_firmware()
6045 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) { in mwl8k_reload_firmware()
6090 hw->extra_tx_headroom -= priv->ap_fw ? REDUCED_TX_HEADROOM : 0; in mwl8k_firmware_load_success()
6108 priv->macids_used = 0; in mwl8k_firmware_load_success()
6135 priv->fw_mutex_depth = 0; in mwl8k_firmware_load_success()
6148 hw->wiphy->interface_modes = 0; in mwl8k_firmware_load_success()
6168 return 0; in mwl8k_firmware_load_success()
6171 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_firmware_load_success()
6173 mwl8k_rxq_deinit(hw, 0); in mwl8k_firmware_load_success()
6232 priv->sram = pci_iomap(pdev, 0, 0x10000); in mwl8k_probe()
6243 priv->regs = pci_iomap(pdev, 1, 0x10000); in mwl8k_probe()
6245 priv->regs = pci_iomap(pdev, 2, 0x10000); in mwl8k_probe()
6279 priv->running_bsses = 0; in mwl8k_probe()
6333 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_remove()
6336 for (i = 0; i < mwl8k_tx_queues(priv); i++) in mwl8k_remove()
6339 mwl8k_rxq_deinit(hw, 0); in mwl8k_remove()