Lines Matching +full:exported +full:- +full:sram
8 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
75 #include "iwl-fh.h"
76 #include "iwl-csr.h"
77 #include "iwl-trans.h"
78 #include "iwl-debug.h"
79 #include "iwl-io.h"
80 #include "iwl-op-mode.h"
81 #include "iwl-drv.h"
102 * @invalid: rxb is in driver ownership - not owned by HW
117 * struct isr_statistics - interrupt statistics
135 * struct iwl_rx_transfer_desc - transfer descriptor
149 * struct iwl_rx_completion_desc - completion descriptor
163 * struct iwl_rxq - Rx queue
166 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
177 * @free_count: Number of pre-allocated buffers in rx_free
186 * @queue: actual rx queue. Not used for multi-rx queue.
223 * struct iwl_rb_allocator - Rx allocator
245 * iwl_get_closed_rb_stts - get closed rb stts from different structs
246 * @rxq - the rxq to get the rb stts from
251 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_get_closed_rb_stts()
252 __le16 *rb_stts = rxq->rb_stts; in iwl_get_closed_rb_stts()
256 struct iwl_rb_status *rb_stts = rxq->rb_stts; in iwl_get_closed_rb_stts()
258 return READ_ONCE(rb_stts->closed_rb_num); in iwl_get_closed_rb_stts()
264 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
280 * enum iwl_shared_irq_flags - level of sharing for irq
290 * enum iwl_image_response_code - image response values
322 * struct iwl_trans_pcie - PCIe transport specific data
340 * @scd_base_addr: scheduler sram base address in SRAM
343 * @pci_dev: basic pci-network driver stuff
347 * @cmd_queue - command queue number
348 * @def_rx_queue - default rx queue number
361 * @msix_entries: array of MSI-X entries
362 * @msix_enabled: true if managed to enable MSI-X
474 return (void *)trans->trans_specific; in IWL_TRANS_GET_PCIE_TRANS()
484 * re-enabled by clearing this bit. This register is defined as in iwl_pcie_clear_irq()
488 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); in iwl_pcie_clear_irq()
526 * ICT - interrupt handling
571 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_disable_interrupts()
572 if (!trans_pcie->msix_enabled) { in _iwl_disable_interrupts()
583 trans_pcie->fh_init_mask); in _iwl_disable_interrupts()
585 trans_pcie->hw_init_mask); in _iwl_disable_interrupts()
598 while (start < fw->num_sec && in iwl_pcie_get_num_sections()
599 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && in iwl_pcie_get_num_sections()
600 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { in iwl_pcie_get_num_sections()
610 struct iwl_self_init_dram *dram = &trans->init_dram; in iwl_pcie_ctxt_info_free_fw_img()
613 if (!dram->fw) { in iwl_pcie_ctxt_info_free_fw_img()
614 WARN_ON(dram->fw_cnt); in iwl_pcie_ctxt_info_free_fw_img()
618 for (i = 0; i < dram->fw_cnt; i++) in iwl_pcie_ctxt_info_free_fw_img()
619 dma_free_coherent(trans->dev, dram->fw[i].size, in iwl_pcie_ctxt_info_free_fw_img()
620 dram->fw[i].block, dram->fw[i].physical); in iwl_pcie_ctxt_info_free_fw_img()
622 kfree(dram->fw); in iwl_pcie_ctxt_info_free_fw_img()
623 dram->fw_cnt = 0; in iwl_pcie_ctxt_info_free_fw_img()
624 dram->fw = NULL; in iwl_pcie_ctxt_info_free_fw_img()
631 spin_lock(&trans_pcie->irq_lock); in iwl_disable_interrupts()
633 spin_unlock(&trans_pcie->irq_lock); in iwl_disable_interrupts()
641 set_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_enable_interrupts()
642 if (!trans_pcie->msix_enabled) { in _iwl_enable_interrupts()
643 trans_pcie->inta_mask = CSR_INI_SET_MASK; in _iwl_enable_interrupts()
644 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in _iwl_enable_interrupts()
650 trans_pcie->hw_mask = trans_pcie->hw_init_mask; in _iwl_enable_interrupts()
651 trans_pcie->fh_mask = trans_pcie->fh_init_mask; in _iwl_enable_interrupts()
653 ~trans_pcie->fh_mask); in _iwl_enable_interrupts()
655 ~trans_pcie->hw_mask); in _iwl_enable_interrupts()
663 spin_lock(&trans_pcie->irq_lock); in iwl_enable_interrupts()
665 spin_unlock(&trans_pcie->irq_lock); in iwl_enable_interrupts()
672 trans_pcie->hw_mask = msk; in iwl_enable_hw_int_msk_msix()
680 trans_pcie->fh_mask = msk; in iwl_enable_fh_int_msk_msix()
688 if (!trans_pcie->msix_enabled) { in iwl_enable_fw_load_int()
689 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; in iwl_enable_fw_load_int()
690 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int()
693 trans_pcie->hw_init_mask); in iwl_enable_fw_load_int()
705 if (!trans_pcie->msix_enabled) { in iwl_enable_fw_load_int_ctx_info()
713 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; in iwl_enable_fw_load_int_ctx_info()
714 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int_ctx_info()
722 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); in iwl_enable_fw_load_int_ctx_info()
729 if (trans_p->shared_vec_mask) { in queue_name()
730 int vec = trans_p->shared_vec_mask & in queue_name()
742 if (i == trans_p->alloc_vecs - 1) in queue_name()
754 if (!trans_pcie->msix_enabled) { in iwl_enable_rfkill_int()
755 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; in iwl_enable_rfkill_int()
756 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_rfkill_int()
759 trans_pcie->fh_init_mask); in iwl_enable_rfkill_int()
764 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { in iwl_enable_rfkill_int()
766 * On 9000-series devices this bit isn't enabled by default, so in iwl_enable_rfkill_int()
768 * to wake up the PCI-E bus for RF-kill interrupts. in iwl_enable_rfkill_int()
781 lockdep_assert_held(&trans_pcie->mutex); in iwl_is_rfkill_set()
783 if (trans_pcie->debug_rfkill == 1) in iwl_is_rfkill_set()
819 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); in iwl_pcie_dbg_on()
853 /* transport gen 2 exported functions */