intel/iwlwifi/iwl-prph.h

8  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10  * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
32  * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
45  *  * Neither the name Intel Corporation nor the names of its
166  * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
168  * 0 -- EDCA BK (background) frames, lowest priority
169  * 1 -- EDCA BE (best effort) frames, normal priority
170  * 2 -- EDCA VI (video) frames, higher priority
171  * 3 -- EDCA VO (voice) and management frames, highest priority
172  * 4 -- unused
173  * 5 -- unused
174  * 6 -- unused
175  * 7 -- Commands
177  * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
179  * channels 0-3 to support 11n aggregation via EDCA DMA channels.
183  * 1)  Scheduler-Ack, in which the scheduler automatically supports a
184  *     block-ack (BA) window of up to 64 TFDs.  In this mode, each queue
187  *     Quality-Of-Service (QOS) priority, destined for a single station.
189  *     In scheduler-ack mode, the scheduler keeps track of the Tx status of
192  *     automatically processes block-acks received from the receiving STA,
193  *     and reschedules un-acked frames to be retransmitted (successful
194  *     Tx completion may end up being out-of-order).
200  * 2)  FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
228  * can keep track of at one time when creating block-ack chains of frames.
229  * Note that "64" matches the number of ack bits in a block-ack packet.
429 /* For UMAG_GEN_HW_STATUS reg check */