Lines Matching +full:reg +full:- +full:names
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
10 * Copyright(c) 2018 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
32 * Copyright(c) 2018 - 2020 Intel Corporation
45 * * Neither the name Intel Corporation nor the names of its
68 #include "iwl-trans.h"
84 * Keep-Warm (KW) buffer base address.
87 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
89 * from going into a power-savings mode that would cause higher DRAM latency,
90 * and possible data over/under-runs, before all Tx/Rx is complete.
94 * automatically invokes keep-warm accesses when normal accesses might not
98 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
106 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
109 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
110 * aligned (address bits 0-7 must be 0).
115 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
130 if (trans->trans_cfg->use_tfh) { in FH_MEM_CBBC_QUEUE()
137 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); in FH_MEM_CBBC_QUEUE()
139 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); in FH_MEM_CBBC_QUEUE()
182 * set to 1 - interrupt is sent to the driver
198 * Note that this register may be configured with non-dword aligned size.
224 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
236 * 31-12: Not used by driver
237 * 11- 0: Index of last filled Rx buffer descriptor
246 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
276 * Physical base address of 8-byte Rx Status buffer.
278 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
285 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
292 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
293 * NOTE: For 256-entry circular buffer, use only bits [7:0].
303 * Rx Config Reg for channel 0 (only channel used)
313 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
315 * 29-24: reserved
316 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
318 * 19-18: reserved
319 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
321 * 15-14: reserved
322 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
323 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
325 * 3- 0: reserved
335 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
338 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
339 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
340 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
392 /* Write index table - shadow registers */
434 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
446 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
459 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
470 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
475 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
492 /* TFDB Area - TFDs buffer table */
515 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
517 * 29- 4: Reserved, set to "0"
519 * 2- 0: Reserved, set to "0"
524 /* Find Control/Status reg for given Tx DMA/FIFO channel */
569 * 31-24: 1 = Channel buffers empty (channel 7:0)
570 * 23-16: 1 = No pending requests (channel 7:0)
583 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
587 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
604 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
610 * it is brought from the memory to TX-FIFO
614 #define RX_POOL_SIZE(rbds) ((rbds) - 1 + \
616 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
625 * struct iwl_rb_status - reserve buffer status
627 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
628 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
629 * @finished_rb_num [0:11] - Indicates the index of the current RB
631 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
645 /* cb size is the exponent - 3 */
646 #define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3)
660 * enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits
700 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
701 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
710 * of (4K - 4). The concatenates all of a TFD's buffers into a single
717 * struct iwl_tfd - Transmit Frame Descriptor (TFD)
719 * @ num_tbs 0-4 number of active tbs
721 * 6-7 padding (not used)
733 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD)
734 * @ num_tbs 0-4 number of active tbs
735 * 5 -15 reserved
748 /* Fixed (non-configurable) rx data from phy */
754 * @tfd_offset 0-12 - tx command byte count
755 * 12-16 - station index
757 * @tfd_offset 0-12 - tx command byte count
758 * 12-13 - number of 64 byte chunks
759 * 14-16 - reserved
768 * @tfd_offset: 0-12 - tx command byte count
769 * 12-13 - number of 64 byte chunks
770 * 14-16 - reserved