intel/iwlwifi/iwl-csr.h

8  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
11  * Copyright(c) 2018 - 2019 Intel Corporation
27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
33  * Copyright(c) 2018 - 2019 Intel Corporation
46  *  * Neither the name Intel Corporation nor the names of its
70  * low power states due to driver-invoked device resets
71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
86 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
100  * 31-16:  Reserved
101  *  15-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
102  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
103  *  1-0:  "Dash" (-) value, as in A-1, etc.
112  * 11:8:  Step (A - 0x0, B - 0x1, etc)
119  * EEPROM and OTP (one-time-programmable) memory reads
133  * UCODE-DRIVER GP (general purpose) mailbox registers.
167 /* Analog phase-lock-loop configuration  */
182  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
183  *  1-0:  "Dash" (-) value, as in C-1, etc.
278  *         Indicates state of (platform's) hardware RF-Kill switch
279  * 26-24:  POWER_SAVE_TYPE
280  *         Indicates current power-saving mode:
281  *         000 -- No power saving
282  *         001 -- MAC power-down
283  *         010 -- PHY (radio) power-down
284  *         011 -- Error
286  *   9-6:  SYS_CONFIG
290  *         Indicates MAC is entering a power-saving sleep power-down.
291  *         Not a good time to access device-internal resources.
294  *         access to device-internal resources.  Host must wait for
295  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
305  *                init or post-power-down restore of internal SRAM memory.
308  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
388 /* EEPROM REG */
402 /* One-time-programmable memory general purpose reg */
403 #define CSR_OTP_GP_REG_DEVICE_SELECT	(0x00010000) /* 0 - EEPROM, 1 - OTP */
404 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE	(0x00020000) /* 0 - absolute, 1 - relative */
408 /* GP REG */
420  * UCODE-DRIVER GP (general purpose) mailbox register 1
431  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
439  *         uCode sets this when preparing a power-saving power-down.
440  *         uCode resets this when power-up is complete and SRAM is sane.
444  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
512  * HBUS (Host-side Bus)
516  * may be powered-down.
533  * data registers auto-increment the address by one dword.
535  *  0-31:  memory address within device
551  *  0-15:  register address (offset) within device
552  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
563  * Per-Tx-queue write pointer (index, really!)
566  *  0-7:  queue write index
567  * 11-8:  queue selector
577  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
598 /* Those are the masks INSIDE the flags bit-field: */