46  /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
78  /* OTP is powered up, use def. CIS, no SPROM */
80  /* OTP is powered up, SPROM is present */
82  /* OTP is powered up, no SPROM */
84  /* OTP is powered down, SPROM is present */
90 /* 43224 chip-specific ChipControl register bits */
109 /* 4331 chip-specific ChipControl register bits */
116  /* sprom/gpio13-15 mux */
120  /* set drive out GPIO_CLK on sprom_cs pin */
126  /* override core control on pipe_AuxClkEnable */
128  /* override core control on pipe_AuxPowerDown */
147 /* 4319 chip-specific ChipStatus register bits */
154  /* use default CIS, OTP is powered up */
156  /* use SPROM, OTP is powered up */
158  /* use OTP, OTP is powered up */
160  /* use SPROM, OTP is powered down */
178 /* 4336 chip-specific ChipStatus register bits */
194 /* 4313 chip-specific ChipStatus register bits */
274 /* PCI config space GPIO 14 for Xtal power-up */
276 /* PCI config space GPIO 15 for PLL power-down */
280 #define PLL_DELAY		150	/* us pll on delay */
282 #define	XTAL_ON_DELAY		1000	/* us crystal power-on delay */
287 #define	NOREV		-1	/* Invalid rev */
290 #define DEFAULT_GPIO_ONTIME	10	/* Default: 10% on */
291 #define DEFAULT_GPIO_OFFTIME	90	/* Default: 10% on */
447 	if (cc->bus->nr_cores == 0)  in ai_buscore_setup()
451 	sii->pub.ccrev = cc->id.rev;  in ai_buscore_setup()
454 	sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));  in ai_buscore_setup()
457 	sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));  in ai_buscore_setup()
460 	if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {  in ai_buscore_setup()
461 		sii->pub.pmucaps = bcma_read32(cc,  in ai_buscore_setup()
463 		sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;  in ai_buscore_setup()
472 	struct si_pub *sih = &sii->pub;  in ai_doattach()
475 	sii->icbus = pbus;  in ai_doattach()
476 	sii->pcibus = pbus->host_pci;  in ai_doattach()
479 	cc = pbus->drv_cc.core;  in ai_doattach()
481 	sih->chip = pbus->chipinfo.id;  in ai_doattach()
482 	sih->chiprev = pbus->chipinfo.rev;  in ai_doattach()
483 	sih->chippkg = pbus->chipinfo.pkg;  in ai_doattach()
484 	sih->boardvendor = pbus->boardinfo.vendor;  in ai_doattach()
485 	sih->boardtype = pbus->boardinfo.type;  in ai_doattach()
550 	cc = sii->icbus->drv_cc.core;  in ai_cc_reg()
562 /* return the slow clock source - LPO, XTAL, or PCI */
594 	 * powered down by dynamic clk control logic.  in ai_clkctl_setdelay()
621 	cc = sii->icbus->drv_cc.core;  in ai_clkctl_init()
653 	cc = sii->icbus->drv_cc.core;  in ai_clkctl_fast_pwrup_delay()
657 			    * 1000000) + (slowminfreq - 1)) / slowminfreq;  in ai_clkctl_fast_pwrup_delay()
677 	cc = sii->icbus->drv_cc.core;  in ai_clkctl_cc()
682 /* Enable BT-COEX & Ex-PA for 4313 */
688 	cc = sii->icbus->drv_cc.core;  in ai_epa_4313war()
702 	if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)  in ai_deviceremoved()
705 	pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w);  in ai_deviceremoved()