Lines Matching full:dev
94 static inline bool b43_nphy_ipa(struct b43_wldev *dev) in b43_nphy_ipa() argument
96 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_ipa()
97 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) || in b43_nphy_ipa()
98 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ)); in b43_nphy_ipa()
102 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) in b43_nphy_get_rx_core_state() argument
104 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >> in b43_nphy_get_rx_core_state()
113 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, in b43_nphy_force_rf_sequence() argument
125 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); in b43_nphy_force_rf_sequence()
129 b43_phy_set(dev, B43_NPHY_RFSEQMODE, in b43_nphy_force_rf_sequence()
131 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); in b43_nphy_force_rf_sequence()
133 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) in b43_nphy_force_rf_sequence()
137 b43err(dev->wl, "RF sequence status timeout\n"); in b43_nphy_force_rf_sequence()
139 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); in b43_nphy_force_rf_sequence()
142 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override_rev19() argument
150 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override_rev7() argument
154 struct b43_phy *phy = &dev->phy; in b43_nphy_rf_ctl_override_rev7()
170 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override); in b43_nphy_rf_ctl_override_rev7()
174 b43err(dev->wl, "Invalid override value %d\n", override); in b43_nphy_rf_ctl_override_rev7()
183 b43_phy_mask(dev, en_addr, ~en_mask); in b43_nphy_rf_ctl_override_rev7()
185 b43_phy_mask(dev, val_addr, ~e->val_mask); in b43_nphy_rf_ctl_override_rev7()
188 b43_phy_set(dev, en_addr, en_mask); in b43_nphy_rf_ctl_override_rev7()
190 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); in b43_nphy_rf_ctl_override_rev7()
197 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, in b43_nphy_rf_ctl_override_one_to_many() argument
201 struct b43_phy *phy = &dev->phy; in b43_nphy_rf_ctl_override_one_to_many()
208 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
209 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
210 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
213 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
214 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
215 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
216 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
217 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
220 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
221 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
222 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
223 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
227 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
229 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
233 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
235 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
241 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override() argument
250 if (dev->phy.rev >= 3) { in b43_nphy_rf_ctl_override()
254 b43err(dev->wl, in b43_nphy_rf_ctl_override()
266 b43_phy_mask(dev, en_addr, ~(field)); in b43_nphy_rf_ctl_override()
267 b43_phy_mask(dev, val_addr, in b43_nphy_rf_ctl_override()
271 b43_phy_set(dev, en_addr, field); in b43_nphy_rf_ctl_override()
272 b43_phy_maskset(dev, val_addr, in b43_nphy_rf_ctl_override()
281 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); in b43_nphy_rf_ctl_override()
284 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); in b43_nphy_rf_ctl_override()
289 b43err(dev->wl, in b43_nphy_rf_ctl_override()
304 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), in b43_nphy_rf_ctl_override()
307 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rf_ctl_override()
308 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_override()
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); in b43_nphy_rf_ctl_override()
316 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev, in b43_nphy_rf_ctl_intc_override_rev7() argument
334 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override_rev7()
335 b43_phy_mask(dev, 0x2ff, ~0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
336 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rf_ctl_intc_override_rev7()
339 b43_phy_maskset(dev, reg, ~0xC0, value << 6); in b43_nphy_rf_ctl_intc_override_rev7()
340 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override_rev7()
342 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); in b43_nphy_rf_ctl_intc_override_rev7()
343 b43_phy_set(dev, 0x2ff, 0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
344 b43_phy_set(dev, 0x2ff, 0x0001); in b43_nphy_rf_ctl_intc_override_rev7()
348 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_rf_ctl_intc_override_rev7()
352 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
353 b43_phy_set(dev, reg, 0x1000); in b43_nphy_rf_ctl_intc_override_rev7()
356 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override_rev7()
365 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
366 b43_phy_mask(dev, reg, ~tmp2); in b43_nphy_rf_ctl_intc_override_rev7()
369 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override_rev7()
378 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
379 b43_phy_mask(dev, reg, ~tmp2); in b43_nphy_rf_ctl_intc_override_rev7()
386 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev, in b43_nphy_rf_ctl_intc_override() argument
393 if (dev->phy.rev >= 7) { in b43_nphy_rf_ctl_intc_override()
394 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value, in b43_nphy_rf_ctl_intc_override()
399 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_rf_ctl_intc_override()
407 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override()
411 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override()
412 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rf_ctl_intc_override()
416 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, in b43_nphy_rf_ctl_intc_override()
418 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, in b43_nphy_rf_ctl_intc_override()
420 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_intc_override()
423 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) { in b43_nphy_rf_ctl_intc_override()
430 b43err(dev->wl, in b43_nphy_rf_ctl_intc_override()
432 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, in b43_nphy_rf_ctl_intc_override()
435 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, in b43_nphy_rf_ctl_intc_override()
437 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rf_ctl_intc_override()
439 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_intc_override()
442 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) { in b43_nphy_rf_ctl_intc_override()
449 b43err(dev->wl, in b43_nphy_rf_ctl_intc_override()
451 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rf_ctl_intc_override()
456 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
463 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
466 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
473 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
476 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
483 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
494 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, in b43_nphy_write_clip_detection() argument
497 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); in b43_nphy_write_clip_detection()
498 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); in b43_nphy_write_clip_detection()
502 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) in b43_nphy_read_clip_detection() argument
504 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); in b43_nphy_read_clip_detection()
505 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); in b43_nphy_read_clip_detection()
509 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) in b43_nphy_classifier() argument
513 if (dev->dev->core_rev == 16) in b43_nphy_classifier()
514 b43_mac_suspend(dev); in b43_nphy_classifier()
516 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); in b43_nphy_classifier()
521 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); in b43_nphy_classifier()
523 if (dev->dev->core_rev == 16) in b43_nphy_classifier()
524 b43_mac_enable(dev); in b43_nphy_classifier()
530 static void b43_nphy_reset_cca(struct b43_wldev *dev) in b43_nphy_reset_cca() argument
534 b43_phy_force_clock(dev, 1); in b43_nphy_reset_cca()
535 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_nphy_reset_cca()
536 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); in b43_nphy_reset_cca()
538 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); in b43_nphy_reset_cca()
539 b43_phy_force_clock(dev, 0); in b43_nphy_reset_cca()
540 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_reset_cca()
544 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) in b43_nphy_stay_in_carrier_search() argument
546 struct b43_phy *phy = &dev->phy; in b43_nphy_stay_in_carrier_search()
552 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); in b43_nphy_stay_in_carrier_search()
553 b43_nphy_classifier(dev, 0x7, in b43_nphy_stay_in_carrier_search()
555 b43_nphy_read_clip_detection(dev, nphy->clip_state); in b43_nphy_stay_in_carrier_search()
556 b43_nphy_write_clip_detection(dev, clip); in b43_nphy_stay_in_carrier_search()
558 b43_nphy_reset_cca(dev); in b43_nphy_stay_in_carrier_search()
561 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); in b43_nphy_stay_in_carrier_search()
562 b43_nphy_write_clip_detection(dev, nphy->clip_state); in b43_nphy_stay_in_carrier_search()
568 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) in b43_nphy_read_lpf_ctl() argument
571 offset = b43_is_40mhz(dev) ? 0x159 : 0x154; in b43_nphy_read_lpf_ctl()
572 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; in b43_nphy_read_lpf_ctl()
576 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) in b43_nphy_adjust_lna_gain_table() argument
578 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_adjust_lna_gain_table()
588 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_adjust_lna_gain_table()
591 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_adjust_lna_gain_table()
595 tmp = 40370 - 315 * dev->phy.channel; in b43_nphy_adjust_lna_gain_table()
597 tmp = 23242 - 224 * dev->phy.channel; in b43_nphy_adjust_lna_gain_table()
617 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); in b43_nphy_adjust_lna_gain_table()
622 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, in b43_nphy_adjust_lna_gain_table()
624 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, in b43_nphy_adjust_lna_gain_table()
628 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_adjust_lna_gain_table()
632 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, in b43_nphy_set_rf_sequence() argument
635 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_set_rf_sequence()
637 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; in b43_nphy_set_rf_sequence()
642 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_set_rf_sequence()
644 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); in b43_nphy_set_rf_sequence()
645 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); in b43_nphy_set_rf_sequence()
648 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); in b43_nphy_set_rf_sequence()
649 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); in b43_nphy_set_rf_sequence()
653 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_set_rf_sequence()
660 static void b43_radio_2057_chantab_upload(struct b43_wldev *dev, in b43_radio_2057_chantab_upload() argument
665 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); in b43_radio_2057_chantab_upload()
666 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); in b43_radio_2057_chantab_upload()
667 …b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextal… in b43_radio_2057_chantab_upload()
668 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); in b43_radio_2057_chantab_upload()
669 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); in b43_radio_2057_chantab_upload()
670 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); in b43_radio_2057_chantab_upload()
671 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); in b43_radio_2057_chantab_upload()
672 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); in b43_radio_2057_chantab_upload()
673 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); in b43_radio_2057_chantab_upload()
674 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); in b43_radio_2057_chantab_upload()
675 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); in b43_radio_2057_chantab_upload()
676 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); in b43_radio_2057_chantab_upload()
677 …b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0… in b43_radio_2057_chantab_upload()
678 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); in b43_radio_2057_chantab_upload()
679 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); in b43_radio_2057_chantab_upload()
680 …b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1… in b43_radio_2057_chantab_upload()
681 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); in b43_radio_2057_chantab_upload()
682 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); in b43_radio_2057_chantab_upload()
685 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); in b43_radio_2057_chantab_upload()
686 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); in b43_radio_2057_chantab_upload()
687 …b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsiz… in b43_radio_2057_chantab_upload()
688 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); in b43_radio_2057_chantab_upload()
689 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); in b43_radio_2057_chantab_upload()
690 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); in b43_radio_2057_chantab_upload()
691 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); in b43_radio_2057_chantab_upload()
692 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); in b43_radio_2057_chantab_upload()
693 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); in b43_radio_2057_chantab_upload()
694 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); in b43_radio_2057_chantab_upload()
695 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); in b43_radio_2057_chantab_upload()
696 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); in b43_radio_2057_chantab_upload()
697 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); in b43_radio_2057_chantab_upload()
698 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); in b43_radio_2057_chantab_upload()
699 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); in b43_radio_2057_chantab_upload()
700 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); in b43_radio_2057_chantab_upload()
701 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); in b43_radio_2057_chantab_upload()
702 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); in b43_radio_2057_chantab_upload()
703 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); in b43_radio_2057_chantab_upload()
704 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); in b43_radio_2057_chantab_upload()
705 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); in b43_radio_2057_chantab_upload()
706 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); in b43_radio_2057_chantab_upload()
707 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); in b43_radio_2057_chantab_upload()
708 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); in b43_radio_2057_chantab_upload()
709 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); in b43_radio_2057_chantab_upload()
710 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); in b43_radio_2057_chantab_upload()
711 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); in b43_radio_2057_chantab_upload()
712 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); in b43_radio_2057_chantab_upload()
716 static void b43_radio_2057_setup(struct b43_wldev *dev, in b43_radio_2057_setup() argument
720 struct b43_phy *phy = &dev->phy; in b43_radio_2057_setup()
722 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g); in b43_radio_2057_setup()
727 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2057_setup()
728 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); in b43_radio_2057_setup()
729 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
730 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
731 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
733 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); in b43_radio_2057_setup()
734 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
735 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
736 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
740 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); in b43_radio_2057_setup()
741 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); in b43_radio_2057_setup()
742 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_radio_2057_setup()
743 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); in b43_radio_2057_setup()
744 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); in b43_radio_2057_setup()
746 if (b43_is_40mhz(dev)) { in b43_radio_2057_setup()
749 b43_radio_write(dev, in b43_radio_2057_setup()
752 b43_radio_write(dev, in b43_radio_2057_setup()
759 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); in b43_radio_2057_setup()
760 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
761 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); in b43_radio_2057_setup()
762 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); in b43_radio_2057_setup()
766 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2057_setup()
770 if (b43_nphy_ipa(dev)) { in b43_radio_2057_setup()
784 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, in b43_radio_2057_setup()
787 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, in b43_radio_2057_setup()
790 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, in b43_radio_2057_setup()
793 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, in b43_radio_2057_setup()
800 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); in b43_radio_2057_setup()
801 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); in b43_radio_2057_setup()
802 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); in b43_radio_2057_setup()
803 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); in b43_radio_2057_setup()
810 static u8 b43_radio_2057_rcal(struct b43_wldev *dev) in b43_radio_2057_rcal() argument
812 struct b43_phy *phy = &dev->phy; in b43_radio_2057_rcal()
834 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]); in b43_radio_2057_rcal()
836 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]); in b43_radio_2057_rcal()
840 b43_phy_write(dev, phy_to_store[i], 0); in b43_radio_2057_rcal()
841 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); in b43_radio_2057_rcal()
842 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); in b43_radio_2057_rcal()
843 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); in b43_radio_2057_rcal()
844 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); in b43_radio_2057_rcal()
845 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); in b43_radio_2057_rcal()
846 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); in b43_radio_2057_rcal()
850 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); in b43_radio_2057_rcal()
852 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
853 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); in b43_radio_2057_rcal()
856 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
857 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
858 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
859 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); in b43_radio_2057_rcal()
862 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
863 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2); in b43_radio_2057_rcal()
864 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
865 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
866 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); in b43_radio_2057_rcal()
867 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
872 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); in b43_radio_2057_rcal()
876 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); in b43_radio_2057_rcal()
880 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); in b43_radio_2057_rcal()
883 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { in b43_radio_2057_rcal()
884 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rcal()
887 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; in b43_radio_2057_rcal()
890 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); in b43_radio_2057_rcal()
894 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]); in b43_radio_2057_rcal()
896 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]); in b43_radio_2057_rcal()
901 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); in b43_radio_2057_rcal()
902 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, in b43_radio_2057_rcal()
906 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); in b43_radio_2057_rcal()
907 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); in b43_radio_2057_rcal()
910 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
913 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
914 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); in b43_radio_2057_rcal()
924 static u16 b43_radio_2057_rccal(struct b43_wldev *dev) in b43_radio_2057_rccal() argument
926 struct b43_phy *phy = &dev->phy; in b43_radio_2057_rccal()
933 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
934 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); in b43_radio_2057_rccal()
936 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
937 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); in b43_radio_2057_rccal()
939 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
942 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
943 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
945 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
947 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
952 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
953 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
955 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
956 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); in b43_radio_2057_rccal()
958 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
962 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
964 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
966 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
968 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
973 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
974 b43_radio_write(dev, R2057_RCCAL_X1, 0x28); in b43_radio_2057_rccal()
975 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
977 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
978 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
979 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); in b43_radio_2057_rccal()
984 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
986 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
988 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rccal()
991 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP); in b43_radio_2057_rccal()
993 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
997 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
999 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
1004 static void b43_radio_2057_init_pre(struct b43_wldev *dev) in b43_radio_2057_init_pre() argument
1006 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU); in b43_radio_2057_init_pre()
1008 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE); in b43_radio_2057_init_pre()
1009 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE); in b43_radio_2057_init_pre()
1010 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU); in b43_radio_2057_init_pre()
1013 static void b43_radio_2057_init_post(struct b43_wldev *dev) in b43_radio_2057_init_post() argument
1015 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); in b43_radio_2057_init_post()
1018 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); in b43_radio_2057_init_post()
1020 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); in b43_radio_2057_init_post()
1021 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); in b43_radio_2057_init_post()
1023 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); in b43_radio_2057_init_post()
1024 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); in b43_radio_2057_init_post()
1026 if (dev->phy.do_full_init) { in b43_radio_2057_init_post()
1027 b43_radio_2057_rcal(dev); in b43_radio_2057_init_post()
1028 b43_radio_2057_rccal(dev); in b43_radio_2057_init_post()
1030 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); in b43_radio_2057_init_post()
1034 static void b43_radio_2057_init(struct b43_wldev *dev) in b43_radio_2057_init() argument
1036 b43_radio_2057_init_pre(dev); in b43_radio_2057_init()
1037 r2057_upload_inittabs(dev); in b43_radio_2057_init()
1038 b43_radio_2057_init_post(dev); in b43_radio_2057_init()
1045 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev, in b43_chantab_radio_2056_upload() argument
1048 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); in b43_chantab_radio_2056_upload()
1049 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); in b43_chantab_radio_2056_upload()
1050 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); in b43_chantab_radio_2056_upload()
1051 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); in b43_chantab_radio_2056_upload()
1052 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); in b43_chantab_radio_2056_upload()
1053 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, in b43_chantab_radio_2056_upload()
1055 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, in b43_chantab_radio_2056_upload()
1057 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3, in b43_chantab_radio_2056_upload()
1059 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, in b43_chantab_radio_2056_upload()
1061 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5, in b43_chantab_radio_2056_upload()
1063 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27, in b43_chantab_radio_2056_upload()
1065 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28, in b43_chantab_radio_2056_upload()
1067 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29, in b43_chantab_radio_2056_upload()
1069 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1, in b43_chantab_radio_2056_upload()
1071 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); in b43_chantab_radio_2056_upload()
1072 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); in b43_chantab_radio_2056_upload()
1073 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); in b43_chantab_radio_2056_upload()
1075 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE, in b43_chantab_radio_2056_upload()
1077 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE, in b43_chantab_radio_2056_upload()
1080 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1082 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1084 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1086 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1088 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1090 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1092 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1094 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1097 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE, in b43_chantab_radio_2056_upload()
1099 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE, in b43_chantab_radio_2056_upload()
1102 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1104 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1106 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1108 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1110 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1112 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1114 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1116 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1121 static void b43_radio_2056_setup(struct b43_wldev *dev, in b43_radio_2056_setup() argument
1124 struct b43_phy *phy = &dev->phy; in b43_radio_2056_setup()
1125 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_radio_2056_setup()
1126 enum nl80211_band band = b43_current_band(dev->wl); in b43_radio_2056_setup()
1134 B43_WARN_ON(dev->phy.rev < 3); in b43_radio_2056_setup()
1137 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 || in b43_radio_2056_setup()
1138 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 || in b43_radio_2056_setup()
1139 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) && in b43_radio_2056_setup()
1140 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC); in b43_radio_2056_setup()
1142 b43_chantab_radio_2056_upload(dev, e); in b43_radio_2056_setup()
1143 b2056_upload_syn_pll_cp2(dev, band == NL80211_BAND_5GHZ); in b43_radio_2056_setup()
1146 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2056_setup()
1147 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1148 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1149 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || in b43_radio_2056_setup()
1150 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { in b43_radio_2056_setup()
1151 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); in b43_radio_2056_setup()
1152 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); in b43_radio_2056_setup()
1154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); in b43_radio_2056_setup()
1155 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); in b43_radio_2056_setup()
1159 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2056_setup()
1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); in b43_radio_2056_setup()
1161 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); in b43_radio_2056_setup()
1162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); in b43_radio_2056_setup()
1163 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); in b43_radio_2056_setup()
1166 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_radio_2056_setup()
1167 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1168 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1169 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); in b43_radio_2056_setup()
1170 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); in b43_radio_2056_setup()
1173 if (dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) { in b43_radio_2056_setup()
1176 if (dev->phy.rev >= 5) { in b43_radio_2056_setup()
1177 b43_radio_write(dev, in b43_radio_2056_setup()
1180 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || in b43_radio_2056_setup()
1181 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { in b43_radio_2056_setup()
1200 b43_radio_write(dev, in b43_radio_2056_setup()
1203 b43_radio_write(dev, in b43_radio_2056_setup()
1206 b43_radio_write(dev, in b43_radio_2056_setup()
1209 b43_radio_write(dev, in b43_radio_2056_setup()
1212 b43_radio_write(dev, in b43_radio_2056_setup()
1215 b43_radio_write(dev, in b43_radio_2056_setup()
1218 b43_radio_write(dev, in b43_radio_2056_setup()
1222 bias = b43_is_40mhz(dev) ? 0x40 : 0x20; in b43_radio_2056_setup()
1223 b43_radio_write(dev, in b43_radio_2056_setup()
1226 b43_radio_write(dev, in b43_radio_2056_setup()
1229 b43_radio_write(dev, in b43_radio_2056_setup()
1233 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); in b43_radio_2056_setup()
1235 } else if (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ) { in b43_radio_2056_setup()
1267 b43_radio_write(dev, in b43_radio_2056_setup()
1269 b43_radio_write(dev, in b43_radio_2056_setup()
1271 b43_radio_write(dev, in b43_radio_2056_setup()
1273 b43_radio_write(dev, in b43_radio_2056_setup()
1275 b43_radio_write(dev, in b43_radio_2056_setup()
1277 b43_radio_write(dev, in b43_radio_2056_setup()
1279 b43_radio_write(dev, in b43_radio_2056_setup()
1281 b43_radio_write(dev, in b43_radio_2056_setup()
1283 b43_radio_write(dev, in b43_radio_2056_setup()
1285 b43_radio_write(dev, in b43_radio_2056_setup()
1292 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); in b43_radio_2056_setup()
1293 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1294 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); in b43_radio_2056_setup()
1295 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1296 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); in b43_radio_2056_setup()
1300 static u8 b43_radio_2056_rcal(struct b43_wldev *dev) in b43_radio_2056_rcal() argument
1302 struct b43_phy *phy = &dev->phy; in b43_radio_2056_rcal()
1308 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2); in b43_radio_2056_rcal()
1309 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); in b43_radio_2056_rcal()
1312 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1314 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); in b43_radio_2056_rcal()
1316 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, in b43_radio_2056_rcal()
1318 b43err(dev->wl, "Radio recalibration timeout\n"); in b43_radio_2056_rcal()
1322 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1323 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT); in b43_radio_2056_rcal()
1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); in b43_radio_2056_rcal()
1326 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2); in b43_radio_2056_rcal()
1331 static void b43_radio_init2056_pre(struct b43_wldev *dev) in b43_radio_init2056_pre() argument
1333 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1336 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1338 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1340 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1344 static void b43_radio_init2056_post(struct b43_wldev *dev) in b43_radio_init2056_post() argument
1346 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); in b43_radio_init2056_post()
1347 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); in b43_radio_init2056_post()
1348 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); in b43_radio_init2056_post()
1350 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); in b43_radio_init2056_post()
1351 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); in b43_radio_init2056_post()
1352 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); in b43_radio_init2056_post()
1353 if (dev->phy.do_full_init) in b43_radio_init2056_post()
1354 b43_radio_2056_rcal(dev); in b43_radio_init2056_post()
1361 static void b43_radio_init2056(struct b43_wldev *dev) in b43_radio_init2056() argument
1363 b43_radio_init2056_pre(dev); in b43_radio_init2056()
1364 b2056_upload_inittabs(dev, 0, 0); in b43_radio_init2056()
1365 b43_radio_init2056_post(dev); in b43_radio_init2056()
1372 static void b43_chantab_radio_upload(struct b43_wldev *dev, in b43_chantab_radio_upload() argument
1375 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); in b43_chantab_radio_upload()
1376 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); in b43_chantab_radio_upload()
1377 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); in b43_chantab_radio_upload()
1378 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); in b43_chantab_radio_upload()
1379 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1381 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); in b43_chantab_radio_upload()
1382 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); in b43_chantab_radio_upload()
1383 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); in b43_chantab_radio_upload()
1384 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); in b43_chantab_radio_upload()
1385 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1387 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); in b43_chantab_radio_upload()
1388 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); in b43_chantab_radio_upload()
1389 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); in b43_chantab_radio_upload()
1390 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); in b43_chantab_radio_upload()
1391 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1393 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); in b43_chantab_radio_upload()
1394 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); in b43_chantab_radio_upload()
1395 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); in b43_chantab_radio_upload()
1396 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); in b43_chantab_radio_upload()
1397 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1399 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); in b43_chantab_radio_upload()
1400 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); in b43_chantab_radio_upload()
1401 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); in b43_chantab_radio_upload()
1402 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); in b43_chantab_radio_upload()
1403 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1405 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); in b43_chantab_radio_upload()
1406 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); in b43_chantab_radio_upload()
1410 static void b43_radio_2055_setup(struct b43_wldev *dev, in b43_radio_2055_setup() argument
1413 B43_WARN_ON(dev->phy.rev >= 3); in b43_radio_2055_setup()
1415 b43_chantab_radio_upload(dev, e); in b43_radio_2055_setup()
1417 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); in b43_radio_2055_setup()
1418 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); in b43_radio_2055_setup()
1419 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_radio_2055_setup()
1420 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); in b43_radio_2055_setup()
1424 static void b43_radio_init2055_pre(struct b43_wldev *dev) in b43_radio_init2055_pre() argument
1426 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1428 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1431 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1435 static void b43_radio_init2055_post(struct b43_wldev *dev) in b43_radio_init2055_post() argument
1437 struct b43_phy_n *nphy = dev->phy.n; in b43_radio_init2055_post()
1438 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_radio_init2055_post()
1442 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM in b43_radio_init2055_post()
1443 && dev->dev->board_type == SSB_BOARD_CB2_4321 in b43_radio_init2055_post()
1444 && dev->dev->board_rev >= 0x41); in b43_radio_init2055_post()
1449 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); in b43_radio_init2055_post()
1451 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1452 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1454 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); in b43_radio_init2055_post()
1455 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); in b43_radio_init2055_post()
1456 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); in b43_radio_init2055_post()
1457 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); in b43_radio_init2055_post()
1458 b43_radio_set(dev, B2055_CAL_MISC, 0x1); in b43_radio_init2055_post()
1460 b43_radio_set(dev, B2055_CAL_MISC, 0x40); in b43_radio_init2055_post()
1461 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) in b43_radio_init2055_post()
1462 b43err(dev->wl, "radio post init timeout\n"); in b43_radio_init2055_post()
1463 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); in b43_radio_init2055_post()
1464 b43_switch_channel(dev, dev->phy.channel); in b43_radio_init2055_post()
1465 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1466 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1467 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1468 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1469 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1470 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1472 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1473 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1475 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1476 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1485 static void b43_radio_init2055(struct b43_wldev *dev) in b43_radio_init2055() argument
1487 b43_radio_init2055_pre(dev); in b43_radio_init2055()
1488 if (b43_status(dev) < B43_STAT_INITIALIZED) { in b43_radio_init2055()
1490 b2055_upload_inittab(dev, 0, 0); in b43_radio_init2055()
1492 bool ghz5 = b43_current_band(dev->wl) == NL80211_BAND_5GHZ; in b43_radio_init2055()
1493 b2055_upload_inittab(dev, ghz5, 0); in b43_radio_init2055()
1495 b43_radio_init2055_post(dev); in b43_radio_init2055()
1503 static int b43_nphy_load_samples(struct b43_wldev *dev, in b43_nphy_load_samples() argument
1505 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_load_samples()
1511 b43err(dev->wl, "allocation for samples loading failed\n"); in b43_nphy_load_samples()
1515 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_load_samples()
1521 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); in b43_nphy_load_samples()
1525 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_load_samples()
1530 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, in b43_nphy_gen_load_samples() argument
1537 bw = b43_is_40mhz(dev) ? 40 : 20; in b43_nphy_gen_load_samples()
1541 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) in b43_nphy_gen_load_samples()
1546 if (b43_is_40mhz(dev)) in b43_nphy_gen_load_samples()
1554 b43err(dev->wl, "allocation for samples generation failed\n"); in b43_nphy_gen_load_samples()
1567 i = b43_nphy_load_samples(dev, samples, len); in b43_nphy_gen_load_samples()
1573 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, in b43_nphy_run_samples() argument
1577 struct b43_phy *phy = &dev->phy; in b43_nphy_run_samples()
1578 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_run_samples()
1583 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_run_samples()
1588 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; in b43_nphy_run_samples()
1589 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; in b43_nphy_run_samples()
1594 u16 value = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_run_samples()
1596 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, in b43_nphy_run_samples()
1599 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, in b43_nphy_run_samples()
1606 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); in b43_nphy_run_samples()
1611 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; in b43_nphy_run_samples()
1612 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); in b43_nphy_run_samples()
1615 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); in b43_nphy_run_samples()
1618 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); in b43_nphy_run_samples()
1620 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); in b43_nphy_run_samples()
1622 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); in b43_nphy_run_samples()
1624 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); in b43_nphy_run_samples()
1626 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); in b43_nphy_run_samples()
1628 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_run_samples()
1629 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); in b43_nphy_run_samples()
1632 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp); in b43_nphy_run_samples()
1635 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) { in b43_nphy_run_samples()
1642 b43err(dev->wl, "run samples timeout\n"); in b43_nphy_run_samples()
1644 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); in b43_nphy_run_samples()
1646 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_run_samples()
1654 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, in b43_nphy_scale_offset_rssi() argument
1669 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1671 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1673 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1675 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1679 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1681 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1683 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1685 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1689 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1691 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1693 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1695 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1699 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); in b43_nphy_scale_offset_rssi()
1701 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); in b43_nphy_scale_offset_rssi()
1703 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); in b43_nphy_scale_offset_rssi()
1705 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); in b43_nphy_scale_offset_rssi()
1709 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1711 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1713 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1715 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1719 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1721 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1725 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1727 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1732 static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code, in b43_nphy_rssi_select_rev19() argument
1738 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rev3_rssi_select() argument
1745 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); in b43_nphy_rev3_rssi_select()
1746 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); in b43_nphy_rev3_rssi_select()
1747 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); in b43_nphy_rev3_rssi_select()
1748 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); in b43_nphy_rev3_rssi_select()
1749 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); in b43_nphy_rev3_rssi_select()
1750 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); in b43_nphy_rev3_rssi_select()
1751 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); in b43_nphy_rev3_rssi_select()
1752 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); in b43_nphy_rev3_rssi_select()
1760 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); in b43_nphy_rev3_rssi_select()
1768 b43_phy_maskset(dev, reg, 0xFCFF, 0); in b43_nphy_rev3_rssi_select()
1773 b43_phy_maskset(dev, reg, 0xFFC3, 0); in b43_nphy_rev3_rssi_select()
1776 val = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 4 : 8; in b43_nphy_rev3_rssi_select()
1781 b43_phy_set(dev, reg, val); in b43_nphy_rev3_rssi_select()
1786 b43_phy_set(dev, reg, 0x0020); in b43_nphy_rev3_rssi_select()
1799 b43_phy_maskset(dev, reg, 0xFCFF, val); in b43_nphy_rev3_rssi_select()
1800 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); in b43_nphy_rev3_rssi_select()
1805 b43_current_band(dev->wl); in b43_nphy_rev3_rssi_select()
1807 if (dev->phy.rev < 7) { in b43_nphy_rev3_rssi_select()
1808 if (b43_nphy_ipa(dev)) in b43_nphy_rev3_rssi_select()
1814 b43_radio_write(dev, reg, val); in b43_nphy_rev3_rssi_select()
1820 b43_phy_set(dev, reg, 0x0200); in b43_nphy_rev3_rssi_select()
1827 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rev2_rssi_select() argument
1851 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1852 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1855 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, in b43_nphy_rev2_rssi_select()
1857 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, in b43_nphy_rev2_rssi_select()
1862 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); in b43_nphy_rev2_rssi_select()
1864 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1867 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rev2_rssi_select()
1872 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1875 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1878 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); in b43_nphy_rev2_rssi_select()
1880 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1885 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rev2_rssi_select()
1890 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1893 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1899 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rssi_select() argument
1902 if (dev->phy.rev >= 19) in b43_nphy_rssi_select()
1903 b43_nphy_rssi_select_rev19(dev, code, type); in b43_nphy_rssi_select()
1904 else if (dev->phy.rev >= 3) in b43_nphy_rssi_select()
1905 b43_nphy_rev3_rssi_select(dev, code, type); in b43_nphy_rssi_select()
1907 b43_nphy_rev2_rssi_select(dev, code, type); in b43_nphy_rssi_select()
1911 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, in b43_nphy_set_rssi_2055_vcm() argument
1918 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, in b43_nphy_set_rssi_2055_vcm()
1920 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1923 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, in b43_nphy_set_rssi_2055_vcm()
1925 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1930 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1933 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1940 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type, in b43_nphy_poll_rssi() argument
1950 if (dev->phy.rev >= 3) { in b43_nphy_poll_rssi()
1951 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1952 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_poll_rssi()
1953 save_regs_phy[2] = b43_phy_read(dev, in b43_nphy_poll_rssi()
1955 save_regs_phy[3] = b43_phy_read(dev, in b43_nphy_poll_rssi()
1957 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); in b43_nphy_poll_rssi()
1958 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_poll_rssi()
1959 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); in b43_nphy_poll_rssi()
1960 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); in b43_nphy_poll_rssi()
1963 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1964 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_poll_rssi()
1965 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_poll_rssi()
1966 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); in b43_nphy_poll_rssi()
1967 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); in b43_nphy_poll_rssi()
1968 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); in b43_nphy_poll_rssi()
1969 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); in b43_nphy_poll_rssi()
1974 b43_nphy_rssi_select(dev, 5, rssi_type); in b43_nphy_poll_rssi()
1976 if (dev->phy.rev < 2) { in b43_nphy_poll_rssi()
1977 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); in b43_nphy_poll_rssi()
1978 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); in b43_nphy_poll_rssi()
1985 if (dev->phy.rev < 2) { in b43_nphy_poll_rssi()
1986 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); in b43_nphy_poll_rssi()
1987 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); in b43_nphy_poll_rssi()
1989 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); in b43_nphy_poll_rssi()
1990 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); in b43_nphy_poll_rssi()
2001 if (dev->phy.rev < 2) in b43_nphy_poll_rssi()
2002 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); in b43_nphy_poll_rssi()
2004 if (dev->phy.rev >= 3) { in b43_nphy_poll_rssi()
2005 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2006 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); in b43_nphy_poll_rssi()
2007 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, in b43_nphy_poll_rssi()
2009 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, in b43_nphy_poll_rssi()
2011 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); in b43_nphy_poll_rssi()
2012 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); in b43_nphy_poll_rssi()
2013 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); in b43_nphy_poll_rssi()
2014 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); in b43_nphy_poll_rssi()
2016 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2017 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); in b43_nphy_poll_rssi()
2018 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); in b43_nphy_poll_rssi()
2019 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); in b43_nphy_poll_rssi()
2020 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); in b43_nphy_poll_rssi()
2021 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); in b43_nphy_poll_rssi()
2022 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); in b43_nphy_poll_rssi()
2029 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) in b43_nphy_rev3_rssi_cal() argument
2031 struct b43_phy *phy = &dev->phy; in b43_nphy_rev3_rssi_cal()
2032 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_rev3_rssi_cal()
2080 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2089 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev3_rssi_cal()
2090 b43_nphy_classifier(dev, 7, 4); in b43_nphy_rev3_rssi_cal()
2091 b43_nphy_read_clip_detection(dev, clip_state); in b43_nphy_rev3_rssi_cal()
2092 b43_nphy_write_clip_detection(dev, clip_off); in b43_nphy_rev3_rssi_cal()
2094 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev3_rssi_cal()
2095 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_rev3_rssi_cal()
2097 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); in b43_nphy_rev3_rssi_cal()
2099 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); in b43_nphy_rev3_rssi_cal()
2100 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); in b43_nphy_rev3_rssi_cal()
2102 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2103 b43_nphy_rf_ctl_override_one_to_many(dev, in b43_nphy_rev3_rssi_cal()
2106 b43_nphy_rf_ctl_override_one_to_many(dev, in b43_nphy_rev3_rssi_cal()
2109 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2110 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2111 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rev3_rssi_cal()
2112 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2114 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2117 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2119 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2123 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2124 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2125 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2126 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2127 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rev3_rssi_cal()
2128 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2129 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2131 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2132 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2136 rx_core_state = b43_nphy_get_rx_core_state(dev); in b43_nphy_rev3_rssi_cal()
2141 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, in b43_nphy_rev3_rssi_cal()
2143 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, in b43_nphy_rev3_rssi_cal()
2148 if (dev->phy.rev >= 7) in b43_nphy_rev3_rssi_cal()
2149 b43_radio_maskset(dev, in b43_nphy_rev3_rssi_cal()
2154 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, in b43_nphy_rev3_rssi_cal()
2156 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8); in b43_nphy_rev3_rssi_cal()
2182 if (dev->phy.rev >= 7) in b43_nphy_rev3_rssi_cal()
2183 b43_radio_maskset(dev, in b43_nphy_rev3_rssi_cal()
2188 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, in b43_nphy_rev3_rssi_cal()
2201 b43_nphy_scale_offset_rssi(dev, 0, offset[i], in b43_nphy_rev3_rssi_cal()
2212 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2214 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2216 b43_nphy_poll_rssi(dev, i, poll_results, 8); in b43_nphy_rev3_rssi_cal()
2224 b43_nphy_scale_offset_rssi(dev, 0, in b43_nphy_rev3_rssi_cal()
2231 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); in b43_nphy_rev3_rssi_cal()
2232 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); in b43_nphy_rev3_rssi_cal()
2234 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev3_rssi_cal()
2236 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); in b43_nphy_rev3_rssi_cal()
2237 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START); in b43_nphy_rev3_rssi_cal()
2238 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); in b43_nphy_rev3_rssi_cal()
2240 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rev3_rssi_cal()
2241 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX); in b43_nphy_rev3_rssi_cal()
2242 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev3_rssi_cal()
2245 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]); in b43_nphy_rev3_rssi_cal()
2248 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_rev3_rssi_cal()
2255 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2256 rssical_radio_regs[0] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2258 rssical_radio_regs[1] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2261 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | in b43_nphy_rev3_rssi_cal()
2263 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 | in b43_nphy_rev3_rssi_cal()
2266 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2267 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2268 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2269 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2270 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X); in b43_nphy_rev3_rssi_cal()
2271 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X); in b43_nphy_rev3_rssi_cal()
2272 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X); in b43_nphy_rev3_rssi_cal()
2273 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X); in b43_nphy_rev3_rssi_cal()
2274 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2275 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2276 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2277 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2280 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_rev3_rssi_cal()
2286 b43_nphy_classifier(dev, 7, class); in b43_nphy_rev3_rssi_cal()
2287 b43_nphy_write_clip_detection(dev, clip_state); in b43_nphy_rev3_rssi_cal()
2291 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type) in b43_nphy_rev2_rssi_cal() argument
2322 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev2_rssi_cal()
2323 b43_nphy_classifier(dev, 7, 4); in b43_nphy_rev2_rssi_cal()
2324 b43_nphy_read_clip_detection(dev, clip_state); in b43_nphy_rev2_rssi_cal()
2325 b43_nphy_write_clip_detection(dev, clip_off); in b43_nphy_rev2_rssi_cal()
2327 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_rev2_rssi_cal()
2332 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev2_rssi_cal()
2333 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2334 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); in b43_nphy_rev2_rssi_cal()
2335 b43_radio_write(dev, B2055_C1_PD_RXTX, val); in b43_nphy_rev2_rssi_cal()
2337 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_rev2_rssi_cal()
2338 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2339 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); in b43_nphy_rev2_rssi_cal()
2340 b43_radio_write(dev, B2055_C2_PD_RXTX, val); in b43_nphy_rev2_rssi_cal()
2342 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2343 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2344 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2345 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2346 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2347 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2349 b43_nphy_rssi_select(dev, 5, type); in b43_nphy_rev2_rssi_cal()
2350 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); in b43_nphy_rev2_rssi_cal()
2351 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); in b43_nphy_rev2_rssi_cal()
2358 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); in b43_nphy_rev2_rssi_cal()
2359 b43_nphy_poll_rssi(dev, type, results[vcm], 8); in b43_nphy_rev2_rssi_cal()
2390 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); in b43_nphy_rev2_rssi_cal()
2406 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, in b43_nphy_rev2_rssi_cal()
2410 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); in b43_nphy_rev2_rssi_cal()
2411 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); in b43_nphy_rev2_rssi_cal()
2415 b43_nphy_rssi_select(dev, 1, N_RSSI_NB); in b43_nphy_rev2_rssi_cal()
2418 b43_nphy_rssi_select(dev, 1, N_RSSI_W1); in b43_nphy_rev2_rssi_cal()
2421 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2424 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2430 b43_nphy_rssi_select(dev, 2, N_RSSI_NB); in b43_nphy_rev2_rssi_cal()
2433 b43_nphy_rssi_select(dev, 2, N_RSSI_W1); in b43_nphy_rev2_rssi_cal()
2436 b43_nphy_rssi_select(dev, 2, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2440 b43_nphy_rssi_select(dev, 0, type); in b43_nphy_rev2_rssi_cal()
2442 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); in b43_nphy_rev2_rssi_cal()
2443 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); in b43_nphy_rev2_rssi_cal()
2444 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); in b43_nphy_rev2_rssi_cal()
2445 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); in b43_nphy_rev2_rssi_cal()
2447 b43_nphy_classifier(dev, 7, class); in b43_nphy_rev2_rssi_cal()
2448 b43_nphy_write_clip_detection(dev, clip_state); in b43_nphy_rev2_rssi_cal()
2451 b43_nphy_reset_cca(dev); in b43_nphy_rev2_rssi_cal()
2458 static void b43_nphy_rssi_cal(struct b43_wldev *dev) in b43_nphy_rssi_cal() argument
2460 if (dev->phy.rev >= 19) { in b43_nphy_rssi_cal()
2462 } else if (dev->phy.rev >= 3) { in b43_nphy_rssi_cal()
2463 b43_nphy_rev3_rssi_cal(dev); in b43_nphy_rssi_cal()
2465 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); in b43_nphy_rssi_cal()
2466 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); in b43_nphy_rssi_cal()
2467 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); in b43_nphy_rssi_cal()
2475 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev19() argument
2480 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev7() argument
2482 struct b43_phy *phy = &dev->phy; in b43_nphy_gain_ctl_workarounds_rev7()
2489 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev3() argument
2491 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_gain_ctl_workarounds_rev3()
2501 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL) in b43_nphy_gain_ctl_workarounds_rev3()
2505 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna); in b43_nphy_gain_ctl_workarounds_rev3()
2506 if (ghz5 && dev->phy.rev >= 5) in b43_nphy_gain_ctl_workarounds_rev3()
2511 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); in b43_nphy_gain_ctl_workarounds_rev3()
2514 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev3()
2515 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev3()
2517 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2519 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2521 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2522 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2523 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2524 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2525 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN, in b43_nphy_gain_ctl_workarounds_rev3()
2527 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN, in b43_nphy_gain_ctl_workarounds_rev3()
2529 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2531 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2533 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2534 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2536 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2537 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2538 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2539 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2540 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2541 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2542 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2543 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2544 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2545 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2546 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2547 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2549 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2550 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2552 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, in b43_nphy_gain_ctl_workarounds_rev3()
2555 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2556 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2557 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2558 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2559 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2560 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2562 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); in b43_nphy_gain_ctl_workarounds_rev3()
2563 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); in b43_nphy_gain_ctl_workarounds_rev3()
2564 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); in b43_nphy_gain_ctl_workarounds_rev3()
2565 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); in b43_nphy_gain_ctl_workarounds_rev3()
2566 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); in b43_nphy_gain_ctl_workarounds_rev3()
2567 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev3()
2569 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev3()
2571 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev3()
2574 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev1_2() argument
2576 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_gain_ctl_workarounds_rev1_2()
2585 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2586 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2589 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2590 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2592 if (!b43_is_40mhz(dev)) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2594 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2595 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2596 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2597 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2601 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev1_2()
2603 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev1_2()
2606 if (!b43_is_40mhz(dev)) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2607 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2609 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2611 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2613 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2617 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev1_2()
2620 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ && in b43_nphy_gain_ctl_workarounds_rev1_2()
2621 b43_is_40mhz(dev)) in b43_nphy_gain_ctl_workarounds_rev1_2()
2626 code = b43_is_40mhz(dev) ? 6 : 7; in b43_nphy_gain_ctl_workarounds_rev1_2()
2630 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2, in b43_nphy_gain_ctl_workarounds_rev1_2()
2632 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2, in b43_nphy_gain_ctl_workarounds_rev1_2()
2635 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2638 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); in b43_nphy_gain_ctl_workarounds_rev1_2()
2640 b43_nphy_adjust_lna_gain_table(dev); in b43_nphy_gain_ctl_workarounds_rev1_2()
2643 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); in b43_nphy_gain_ctl_workarounds_rev1_2()
2644 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2645 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2646 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2647 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2649 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); in b43_nphy_gain_ctl_workarounds_rev1_2()
2650 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2651 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2652 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2653 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2655 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2658 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_gain_ctl_workarounds_rev1_2()
2662 if (dev->phy.rev == 2) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2664 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_gain_ctl_workarounds_rev1_2()
2668 b43_phy_write(dev, in b43_nphy_gain_ctl_workarounds_rev1_2()
2674 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); in b43_nphy_gain_ctl_workarounds_rev1_2()
2675 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, in b43_nphy_gain_ctl_workarounds_rev1_2()
2679 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_gain_ctl_workarounds_rev1_2()
2680 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); in b43_nphy_gain_ctl_workarounds_rev1_2()
2684 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds() argument
2686 if (dev->phy.rev >= 19) in b43_nphy_gain_ctl_workarounds()
2687 b43_nphy_gain_ctl_workarounds_rev19(dev); in b43_nphy_gain_ctl_workarounds()
2688 else if (dev->phy.rev >= 7) in b43_nphy_gain_ctl_workarounds()
2689 b43_nphy_gain_ctl_workarounds_rev7(dev); in b43_nphy_gain_ctl_workarounds()
2690 else if (dev->phy.rev >= 3) in b43_nphy_gain_ctl_workarounds()
2691 b43_nphy_gain_ctl_workarounds_rev3(dev); in b43_nphy_gain_ctl_workarounds()
2693 b43_nphy_gain_ctl_workarounds_rev1_2(dev); in b43_nphy_gain_ctl_workarounds()
2696 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) in b43_nphy_workarounds_rev7plus() argument
2698 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev7plus()
2699 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds_rev7plus()
2727 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev7plus()
2728 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); in b43_nphy_workarounds_rev7plus()
2729 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev7plus()
2730 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); in b43_nphy_workarounds_rev7plus()
2731 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); in b43_nphy_workarounds_rev7plus()
2732 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev7plus()
2735 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); in b43_nphy_workarounds_rev7plus()
2736 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); in b43_nphy_workarounds_rev7plus()
2737 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); in b43_nphy_workarounds_rev7plus()
2738 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); in b43_nphy_workarounds_rev7plus()
2739 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); in b43_nphy_workarounds_rev7plus()
2740 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); in b43_nphy_workarounds_rev7plus()
2741 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); in b43_nphy_workarounds_rev7plus()
2742 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); in b43_nphy_workarounds_rev7plus()
2743 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); in b43_nphy_workarounds_rev7plus()
2744 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); in b43_nphy_workarounds_rev7plus()
2745 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); in b43_nphy_workarounds_rev7plus()
2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2747 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2748 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2749 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2750 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2751 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2755 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); in b43_nphy_workarounds_rev7plus()
2756 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); in b43_nphy_workarounds_rev7plus()
2758 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); in b43_nphy_workarounds_rev7plus()
2759 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); in b43_nphy_workarounds_rev7plus()
2763 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); in b43_nphy_workarounds_rev7plus()
2765 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); in b43_nphy_workarounds_rev7plus()
2767 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); in b43_nphy_workarounds_rev7plus()
2768 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); in b43_nphy_workarounds_rev7plus()
2769 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev7plus()
2771 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev7plus()
2772 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2773 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2775 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, in b43_nphy_workarounds_rev7plus()
2777 if (b43_nphy_ipa(dev)) in b43_nphy_workarounds_rev7plus()
2778 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev7plus()
2781 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2782 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2785 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2786 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2787 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2790 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL); in b43_nphy_workarounds_rev7plus()
2791 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL); in b43_nphy_workarounds_rev7plus()
2793 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev7plus()
2794 bool ghz2 = b43_current_band(dev->wl) == NL80211_BAND_2GHZ; in b43_nphy_workarounds_rev7plus()
2799 if (phy->rev == 8 && b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev7plus()
2822 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2933 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), in b43_nphy_workarounds_rev7plus()
2935 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), in b43_nphy_workarounds_rev7plus()
2937 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), in b43_nphy_workarounds_rev7plus()
2939 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), in b43_nphy_workarounds_rev7plus()
2941 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), in b43_nphy_workarounds_rev7plus()
2943 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), in b43_nphy_workarounds_rev7plus()
2945 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), in b43_nphy_workarounds_rev7plus()
2947 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), in b43_nphy_workarounds_rev7plus()
2952 b43_phy_write(dev, 0x32F, 0x3); in b43_nphy_workarounds_rev7plus()
2955 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); in b43_nphy_workarounds_rev7plus()
2960 b43_radio_write(dev, 0x5, 0x05); in b43_nphy_workarounds_rev7plus()
2961 b43_radio_write(dev, 0x6, 0x30); in b43_nphy_workarounds_rev7plus()
2962 b43_radio_write(dev, 0x7, 0x00); in b43_nphy_workarounds_rev7plus()
2963 b43_radio_set(dev, 0x4f, 0x1); in b43_nphy_workarounds_rev7plus()
2964 b43_radio_set(dev, 0xd4, 0x1); in b43_nphy_workarounds_rev7plus()
2973 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2976 b43_radio_write(dev, 0x5F, bias); in b43_nphy_workarounds_rev7plus()
2977 b43_radio_write(dev, 0x64, conv); in b43_nphy_workarounds_rev7plus()
2978 b43_radio_write(dev, 0x66, filt); in b43_nphy_workarounds_rev7plus()
2980 b43_radio_write(dev, 0xE8, bias); in b43_nphy_workarounds_rev7plus()
2981 b43_radio_write(dev, 0xE9, conv); in b43_nphy_workarounds_rev7plus()
2982 b43_radio_write(dev, 0xEB, filt); in b43_nphy_workarounds_rev7plus()
2988 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev7plus()
2989 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2994 b43_radio_write(dev, 0x51, in b43_nphy_workarounds_rev7plus()
2997 b43_radio_write(dev, 0xd6, in b43_nphy_workarounds_rev7plus()
3005 b43_radio_write(dev, 0x64, in b43_nphy_workarounds_rev7plus()
3007 b43_radio_write(dev, 0x5F, in b43_nphy_workarounds_rev7plus()
3009 b43_radio_write(dev, 0x66, in b43_nphy_workarounds_rev7plus()
3011 b43_radio_write(dev, 0x59, in b43_nphy_workarounds_rev7plus()
3013 b43_radio_write(dev, 0x80, in b43_nphy_workarounds_rev7plus()
3016 b43_radio_write(dev, 0x69, in b43_nphy_workarounds_rev7plus()
3018 b43_radio_write(dev, 0xE8, in b43_nphy_workarounds_rev7plus()
3020 b43_radio_write(dev, 0xEB, in b43_nphy_workarounds_rev7plus()
3022 b43_radio_write(dev, 0xDE, in b43_nphy_workarounds_rev7plus()
3024 b43_radio_write(dev, 0x105, in b43_nphy_workarounds_rev7plus()
3031 if (!b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev7plus()
3032 b43_radio_write(dev, 0x5F, 0x14); in b43_nphy_workarounds_rev7plus()
3033 b43_radio_write(dev, 0xE8, 0x12); in b43_nphy_workarounds_rev7plus()
3035 b43_radio_write(dev, 0x5F, 0x16); in b43_nphy_workarounds_rev7plus()
3036 b43_radio_write(dev, 0xE8, 0x16); in b43_nphy_workarounds_rev7plus()
3043 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); in b43_nphy_workarounds_rev7plus()
3044 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); in b43_nphy_workarounds_rev7plus()
3045 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); in b43_nphy_workarounds_rev7plus()
3046 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); in b43_nphy_workarounds_rev7plus()
3047 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); in b43_nphy_workarounds_rev7plus()
3048 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); in b43_nphy_workarounds_rev7plus()
3049 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); in b43_nphy_workarounds_rev7plus()
3050 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); in b43_nphy_workarounds_rev7plus()
3058 b43_radio_write(dev, 0x7D, 0xFF); in b43_nphy_workarounds_rev7plus()
3059 b43_radio_write(dev, 0xFE, 0xFF); in b43_nphy_workarounds_rev7plus()
3066 b43_radio_write(dev, 0x5c, 0x61); in b43_nphy_workarounds_rev7plus()
3067 b43_radio_write(dev, 0x51, 0x70); in b43_nphy_workarounds_rev7plus()
3069 b43_radio_write(dev, 0xe1, 0x61); in b43_nphy_workarounds_rev7plus()
3070 b43_radio_write(dev, 0xd6, 0x70); in b43_nphy_workarounds_rev7plus()
3077 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); in b43_nphy_workarounds_rev7plus()
3078 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); in b43_nphy_workarounds_rev7plus()
3081 b43_radio_write(dev, 0x1a1, 0x00); in b43_nphy_workarounds_rev7plus()
3082 b43_radio_write(dev, 0x1a2, 0x3f); in b43_nphy_workarounds_rev7plus()
3083 b43_radio_write(dev, 0x1a6, 0x3f); in b43_nphy_workarounds_rev7plus()
3085 b43_radio_write(dev, 0x1a7, 0x00); in b43_nphy_workarounds_rev7plus()
3086 b43_radio_write(dev, 0x1ab, 0x3f); in b43_nphy_workarounds_rev7plus()
3087 b43_radio_write(dev, 0x1ac, 0x3f); in b43_nphy_workarounds_rev7plus()
3091 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); in b43_nphy_workarounds_rev7plus()
3092 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); in b43_nphy_workarounds_rev7plus()
3093 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); in b43_nphy_workarounds_rev7plus()
3094 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); in b43_nphy_workarounds_rev7plus()
3096 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); in b43_nphy_workarounds_rev7plus()
3097 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); in b43_nphy_workarounds_rev7plus()
3098 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); in b43_nphy_workarounds_rev7plus()
3099 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); in b43_nphy_workarounds_rev7plus()
3100 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); in b43_nphy_workarounds_rev7plus()
3101 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); in b43_nphy_workarounds_rev7plus()
3103 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); in b43_nphy_workarounds_rev7plus()
3104 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); in b43_nphy_workarounds_rev7plus()
3105 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); in b43_nphy_workarounds_rev7plus()
3106 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); in b43_nphy_workarounds_rev7plus()
3109 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); in b43_nphy_workarounds_rev7plus()
3111 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); in b43_nphy_workarounds_rev7plus()
3112 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3113 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); in b43_nphy_workarounds_rev7plus()
3114 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); in b43_nphy_workarounds_rev7plus()
3115 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3116 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); in b43_nphy_workarounds_rev7plus()
3117 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); in b43_nphy_workarounds_rev7plus()
3119 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3120 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3121 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3123 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3124 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3125 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3127 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev7plus()
3130 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, in b43_nphy_workarounds_rev7plus()
3132 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, in b43_nphy_workarounds_rev7plus()
3134 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4, in b43_nphy_workarounds_rev7plus()
3136 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4, in b43_nphy_workarounds_rev7plus()
3141 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) in b43_nphy_workarounds_rev3plus() argument
3143 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_workarounds_rev3plus()
3144 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev3plus()
3176 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); in b43_nphy_workarounds_rev3plus()
3177 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); in b43_nphy_workarounds_rev3plus()
3179 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev3plus()
3181 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev3plus()
3183 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev3plus()
3184 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); in b43_nphy_workarounds_rev3plus()
3185 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev3plus()
3186 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); in b43_nphy_workarounds_rev3plus()
3187 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); in b43_nphy_workarounds_rev3plus()
3188 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev3plus()
3190 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3191 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3194 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, in b43_nphy_workarounds_rev3plus()
3198 if (b43_nphy_ipa(dev)) in b43_nphy_workarounds_rev3plus()
3199 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev3plus()
3203 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev3plus()
3208 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, in b43_nphy_workarounds_rev3plus()
3212 tmp16 = (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? in b43_nphy_workarounds_rev3plus()
3214 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); in b43_nphy_workarounds_rev3plus()
3216 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); in b43_nphy_workarounds_rev3plus()
3218 if (!b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev3plus()
3219 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); in b43_nphy_workarounds_rev3plus()
3220 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); in b43_nphy_workarounds_rev3plus()
3222 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); in b43_nphy_workarounds_rev3plus()
3223 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); in b43_nphy_workarounds_rev3plus()
3226 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev3plus()
3228 b43_ntab_write(dev, B43_NTAB16(8, 0), 2); in b43_nphy_workarounds_rev3plus()
3229 b43_ntab_write(dev, B43_NTAB16(8, 16), 2); in b43_nphy_workarounds_rev3plus()
3231 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_workarounds_rev3plus()
3239 if (!(dev->phy.rev >= 4 && in b43_nphy_workarounds_rev3plus()
3240 b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) in b43_nphy_workarounds_rev3plus()
3245 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3246 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3247 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3248 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3251 if (dev->phy.rev >= 6) { in b43_nphy_workarounds_rev3plus()
3252 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_workarounds_rev3plus()
3257 } else if (dev->phy.rev == 5) { in b43_nphy_workarounds_rev3plus()
3261 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3262 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3263 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3264 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3268 if (b43_current_band(dev->wl) != NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev3plus()
3289 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3290 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3292 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3293 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3297 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3298 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3299 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3300 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3301 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3302 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3303 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3304 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3305 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3306 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3307 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3308 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3313 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) || in b43_nphy_workarounds_rev3plus()
3315 b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) in b43_nphy_workarounds_rev3plus()
3319 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); in b43_nphy_workarounds_rev3plus()
3320 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); in b43_nphy_workarounds_rev3plus()
3321 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); in b43_nphy_workarounds_rev3plus()
3323 if (dev->phy.rev == 4 && in b43_nphy_workarounds_rev3plus()
3324 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_workarounds_rev3plus()
3325 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, in b43_nphy_workarounds_rev3plus()
3327 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, in b43_nphy_workarounds_rev3plus()
3332 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); in b43_nphy_workarounds_rev3plus()
3333 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); in b43_nphy_workarounds_rev3plus()
3334 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); in b43_nphy_workarounds_rev3plus()
3335 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); in b43_nphy_workarounds_rev3plus()
3336 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3337 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3338 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3339 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3340 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3341 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3342 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3343 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3345 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) { in b43_nphy_workarounds_rev3plus()
3350 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) in b43_nphy_workarounds_rev1_2() argument
3352 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev1_2()
3353 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds_rev1_2()
3363 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) { in b43_nphy_workarounds_rev1_2()
3368 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ && in b43_nphy_workarounds_rev1_2()
3370 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3371 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3373 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3374 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3377 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); in b43_nphy_workarounds_rev1_2()
3378 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); in b43_nphy_workarounds_rev1_2()
3379 if (dev->phy.rev < 3) { in b43_nphy_workarounds_rev1_2()
3380 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3381 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3384 if (dev->phy.rev < 2) { in b43_nphy_workarounds_rev1_2()
3385 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); in b43_nphy_workarounds_rev1_2()
3386 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); in b43_nphy_workarounds_rev1_2()
3387 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3388 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3389 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); in b43_nphy_workarounds_rev1_2()
3390 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); in b43_nphy_workarounds_rev1_2()
3393 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_workarounds_rev1_2()
3394 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_workarounds_rev1_2()
3395 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_workarounds_rev1_2()
3396 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_workarounds_rev1_2()
3398 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); in b43_nphy_workarounds_rev1_2()
3399 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); in b43_nphy_workarounds_rev1_2()
3401 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev1_2()
3403 if (dev->phy.rev < 2) { in b43_nphy_workarounds_rev1_2()
3404 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) in b43_nphy_workarounds_rev1_2()
3405 b43_hf_write(dev, b43_hf_read(dev) | in b43_nphy_workarounds_rev1_2()
3407 } else if (dev->phy.rev == 2) { in b43_nphy_workarounds_rev1_2()
3408 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); in b43_nphy_workarounds_rev1_2()
3409 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); in b43_nphy_workarounds_rev1_2()
3412 if (dev->phy.rev < 2) in b43_nphy_workarounds_rev1_2()
3413 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, in b43_nphy_workarounds_rev1_2()
3417 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); in b43_nphy_workarounds_rev1_2()
3418 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); in b43_nphy_workarounds_rev1_2()
3419 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); in b43_nphy_workarounds_rev1_2()
3420 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); in b43_nphy_workarounds_rev1_2()
3421 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); in b43_nphy_workarounds_rev1_2()
3422 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); in b43_nphy_workarounds_rev1_2()
3424 if (dev->phy.rev < 3) { in b43_nphy_workarounds_rev1_2()
3425 b43_phy_mask(dev, B43_NPHY_PIL_DW1, in b43_nphy_workarounds_rev1_2()
3427 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); in b43_nphy_workarounds_rev1_2()
3428 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); in b43_nphy_workarounds_rev1_2()
3429 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); in b43_nphy_workarounds_rev1_2()
3432 if (dev->phy.rev == 2) in b43_nphy_workarounds_rev1_2()
3433 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, in b43_nphy_workarounds_rev1_2()
3438 static void b43_nphy_workarounds(struct b43_wldev *dev) in b43_nphy_workarounds() argument
3440 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds()
3443 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_workarounds()
3444 b43_nphy_classifier(dev, 1, 0); in b43_nphy_workarounds()
3446 b43_nphy_classifier(dev, 1, 1); in b43_nphy_workarounds()
3449 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_workarounds()
3451 b43_phy_set(dev, B43_NPHY_IQFLIP, in b43_nphy_workarounds()
3455 if (dev->phy.rev >= 7) in b43_nphy_workarounds()
3456 b43_nphy_workarounds_rev7plus(dev); in b43_nphy_workarounds()
3457 else if (dev->phy.rev >= 3) in b43_nphy_workarounds()
3458 b43_nphy_workarounds_rev3plus(dev); in b43_nphy_workarounds()
3460 b43_nphy_workarounds_rev1_2(dev); in b43_nphy_workarounds()
3463 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_workarounds()
3474 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, in b43_nphy_tx_tone() argument
3477 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); in b43_nphy_tx_tone()
3480 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, in b43_nphy_tx_tone()
3486 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) in b43_nphy_update_txrx_chain() argument
3488 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_update_txrx_chain()
3501 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, in b43_nphy_update_txrx_chain()
3506 b43_phy_set(dev, B43_NPHY_RFSEQMODE, in b43_nphy_update_txrx_chain()
3509 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, in b43_nphy_update_txrx_chain()
3514 static void b43_nphy_stop_playback(struct b43_wldev *dev) in b43_nphy_stop_playback() argument
3516 struct b43_phy *phy = &dev->phy; in b43_nphy_stop_playback()
3517 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_stop_playback()
3521 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_stop_playback()
3523 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); in b43_nphy_stop_playback()
3525 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); in b43_nphy_stop_playback()
3527 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_stop_playback()
3529 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); in b43_nphy_stop_playback()
3533 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); in b43_nphy_stop_playback()
3539 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, in b43_nphy_stop_playback()
3542 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); in b43_nphy_stop_playback()
3547 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_stop_playback()
3551 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, in b43_nphy_iq_cal_gain_params() argument
3555 struct b43_phy *phy = &dev->phy; in b43_nphy_iq_cal_gain_params()
3559 if (dev->phy.rev >= 3) { in b43_nphy_iq_cal_gain_params()
3578 indx = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? in b43_nphy_iq_cal_gain_params()
3600 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) in b43_nphy_tx_power_ctrl() argument
3602 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctrl()
3603 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctrl()
3606 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_tx_power_ctrl()
3609 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_tx_power_ctrl()
3613 if (dev->phy.rev >= 3 && in b43_nphy_tx_power_ctrl()
3614 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & in b43_nphy_tx_power_ctrl()
3619 nphy->tx_pwr_idx[0] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3621 nphy->tx_pwr_idx[1] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3625 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); in b43_nphy_tx_power_ctrl()
3627 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3629 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); in b43_nphy_tx_power_ctrl()
3631 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3634 if (dev->phy.rev >= 3) in b43_nphy_tx_power_ctrl()
3636 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); in b43_nphy_tx_power_ctrl()
3638 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3639 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_ctrl()
3640 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_ctrl()
3642 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_ctrl()
3645 if (dev->phy.rev == 2) in b43_nphy_tx_power_ctrl()
3646 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_nphy_tx_power_ctrl()
3648 else if (dev->phy.rev < 2) in b43_nphy_tx_power_ctrl()
3649 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_nphy_tx_power_ctrl()
3652 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) in b43_nphy_tx_power_ctrl()
3653 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); in b43_nphy_tx_power_ctrl()
3655 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, in b43_nphy_tx_power_ctrl()
3657 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, in b43_nphy_tx_power_ctrl()
3664 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3669 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); in b43_nphy_tx_power_ctrl()
3675 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3678 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctrl()
3682 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3686 b43_phy_maskset(dev, in b43_nphy_tx_power_ctrl()
3693 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3697 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3700 if (dev->phy.rev > 1) in b43_nphy_tx_power_ctrl()
3701 b43_phy_maskset(dev, in b43_nphy_tx_power_ctrl()
3711 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3712 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); in b43_nphy_tx_power_ctrl()
3713 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); in b43_nphy_tx_power_ctrl()
3715 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); in b43_nphy_tx_power_ctrl()
3718 if (dev->phy.rev == 2) in b43_nphy_tx_power_ctrl()
3719 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); in b43_nphy_tx_power_ctrl()
3720 else if (dev->phy.rev < 2) in b43_nphy_tx_power_ctrl()
3721 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); in b43_nphy_tx_power_ctrl()
3723 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) in b43_nphy_tx_power_ctrl()
3724 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); in b43_nphy_tx_power_ctrl()
3726 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_ctrl()
3727 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); in b43_nphy_tx_power_ctrl()
3728 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); in b43_nphy_tx_power_ctrl()
3733 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_ctrl()
3737 static void b43_nphy_tx_power_fix(struct b43_wldev *dev) in b43_nphy_tx_power_fix() argument
3739 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_fix()
3740 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_fix()
3741 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_tx_power_fix()
3750 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_tx_power_fix()
3753 if (dev->phy.rev >= 7) { in b43_nphy_tx_power_fix()
3755 } else if (dev->phy.rev >= 3) { in b43_nphy_tx_power_fix()
3762 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_tx_power_fix()
3779 if (dev->phy.rev < 7 && in b43_nphy_tx_power_fix()
3791 const u32 *table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_tx_power_fix()
3797 if (dev->phy.rev >= 3) in b43_nphy_tx_power_fix()
3802 if (dev->phy.rev >= 7) in b43_nphy_tx_power_fix()
3808 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_fix()
3810 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_fix()
3812 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_fix()
3814 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_fix()
3818 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); in b43_nphy_tx_power_fix()
3820 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); in b43_nphy_tx_power_fix()
3822 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); in b43_nphy_tx_power_fix()
3824 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); in b43_nphy_tx_power_fix()
3829 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); in b43_nphy_tx_power_fix()
3831 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_fix()
3835 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, in b43_nphy_tx_power_fix()
3837 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); in b43_nphy_tx_power_fix()
3838 b43_phy_set(dev, reg, 0x4); in b43_nphy_tx_power_fix()
3842 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); in b43_nphy_tx_power_fix()
3845 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_fix()
3848 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev) in b43_nphy_ipa_internal_tssi_setup() argument
3850 struct b43_phy *phy = &dev->phy; in b43_nphy_ipa_internal_tssi_setup()
3860 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_ipa_internal_tssi_setup()
3861 b43_radio_write(dev, r + 0x5, 0x5); in b43_nphy_ipa_internal_tssi_setup()
3862 b43_radio_write(dev, r + 0x9, 0xE); in b43_nphy_ipa_internal_tssi_setup()
3864 b43_radio_write(dev, r + 0xA, 0); in b43_nphy_ipa_internal_tssi_setup()
3866 b43_radio_write(dev, r + 0xB, 1); in b43_nphy_ipa_internal_tssi_setup()
3868 b43_radio_write(dev, r + 0xB, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3870 b43_radio_write(dev, r + 0x5, 0x9); in b43_nphy_ipa_internal_tssi_setup()
3871 b43_radio_write(dev, r + 0x9, 0xC); in b43_nphy_ipa_internal_tssi_setup()
3872 b43_radio_write(dev, r + 0xB, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3874 b43_radio_write(dev, r + 0xA, 1); in b43_nphy_ipa_internal_tssi_setup()
3876 b43_radio_write(dev, r + 0xA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3878 b43_radio_write(dev, r + 0x6, 0); in b43_nphy_ipa_internal_tssi_setup()
3879 b43_radio_write(dev, r + 0x7, 0); in b43_nphy_ipa_internal_tssi_setup()
3880 b43_radio_write(dev, r + 0x8, 3); in b43_nphy_ipa_internal_tssi_setup()
3881 b43_radio_write(dev, r + 0xC, 0); in b43_nphy_ipa_internal_tssi_setup()
3884 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_ipa_internal_tssi_setup()
3885 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); in b43_nphy_ipa_internal_tssi_setup()
3887 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); in b43_nphy_ipa_internal_tssi_setup()
3888 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); in b43_nphy_ipa_internal_tssi_setup()
3889 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); in b43_nphy_ipa_internal_tssi_setup()
3894 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); in b43_nphy_ipa_internal_tssi_setup()
3895 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); in b43_nphy_ipa_internal_tssi_setup()
3896 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3); in b43_nphy_ipa_internal_tssi_setup()
3897 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); in b43_nphy_ipa_internal_tssi_setup()
3898 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8); in b43_nphy_ipa_internal_tssi_setup()
3899 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); in b43_nphy_ipa_internal_tssi_setup()
3900 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); in b43_nphy_ipa_internal_tssi_setup()
3901 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_ipa_internal_tssi_setup()
3902 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, in b43_nphy_ipa_internal_tssi_setup()
3905 b43_radio_write(dev, r | B2056_TX_TSSIA, in b43_nphy_ipa_internal_tssi_setup()
3908 b43_radio_write(dev, r | B2056_TX_TSSIG, in b43_nphy_ipa_internal_tssi_setup()
3911 b43_radio_write(dev, r | B2056_TX_TSSIG, in b43_nphy_ipa_internal_tssi_setup()
3913 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, in b43_nphy_ipa_internal_tssi_setup()
3916 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, in b43_nphy_ipa_internal_tssi_setup()
3918 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3919 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3920 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, in b43_nphy_ipa_internal_tssi_setup()
3932 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) in b43_nphy_tx_power_ctl_idle_tssi() argument
3934 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctl_idle_tssi()
3935 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctl_idle_tssi()
3943 if (b43_nphy_ipa(dev)) in b43_nphy_tx_power_ctl_idle_tssi()
3944 b43_nphy_ipa_internal_tssi_setup(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3947 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3949 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3951 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); in b43_nphy_tx_power_ctl_idle_tssi()
3953 b43_nphy_stop_playback(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3954 b43_nphy_tx_tone(dev, 4000, 0, false, false, false); in b43_nphy_tx_power_ctl_idle_tssi()
3956 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1); in b43_nphy_tx_power_ctl_idle_tssi()
3957 b43_nphy_stop_playback(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3959 b43_nphy_rssi_select(dev, 0, N_RSSI_W1); in b43_nphy_tx_power_ctl_idle_tssi()
3962 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3964 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3966 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); in b43_nphy_tx_power_ctl_idle_tssi()
3983 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev) in b43_nphy_tx_prepare_adjusted_power_table() argument
3985 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_prepare_adjusted_power_table()
4011 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) { in b43_nphy_tx_prepare_adjusted_power_table()
4015 idx = b43_is_40mhz(dev) ? 52 : 4; in b43_nphy_tx_prepare_adjusted_power_table()
4019 idx = b43_is_40mhz(dev) ? 76 : 28; in b43_nphy_tx_prepare_adjusted_power_table()
4022 idx = b43_is_40mhz(dev) ? 84 : 36; in b43_nphy_tx_prepare_adjusted_power_table()
4025 idx = b43_is_40mhz(dev) ? 92 : 44; in b43_nphy_tx_prepare_adjusted_power_table()
4044 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev) in b43_nphy_tx_power_ctl_setup() argument
4046 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctl_setup()
4047 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctl_setup()
4048 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_tx_power_ctl_setup()
4062 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_tx_power_ctl_setup()
4063 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4064 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_tx_power_ctl_setup()
4069 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_tx_power_ctl_setup()
4071 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN); in b43_nphy_tx_power_ctl_setup()
4072 if (dev->phy.rev >= 3) in b43_nphy_tx_power_ctl_setup()
4073 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4076 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4079 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_tx_power_ctl_setup()
4080 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4090 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_tx_power_ctl_setup()
4132 ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr); in b43_nphy_tx_power_ctl_setup()
4138 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctl_setup()
4140 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); in b43_nphy_tx_power_ctl_setup()
4141 if (dev->phy.rev >= 7) { in b43_nphy_tx_power_ctl_setup()
4144 if (b43_nphy_ipa(dev)) in b43_nphy_tx_power_ctl_setup()
4145 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? 0xE : 0xC); in b43_nphy_tx_power_ctl_setup()
4148 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_ctl_setup()
4149 tmp = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 0xC : 0xE; in b43_nphy_tx_power_ctl_setup()
4150 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4152 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4155 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4157 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4163 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_tx_power_ctl_setup()
4164 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4165 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_tx_power_ctl_setup()
4172 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4174 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctl_setup()
4177 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4179 if (dev->phy.rev > 1) in b43_nphy_tx_power_ctl_setup()
4180 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctl_setup()
4184 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_tx_power_ctl_setup()
4185 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4187 b43_phy_write(dev, B43_NPHY_TXPCTL_N, in b43_nphy_tx_power_ctl_setup()
4190 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI, in b43_nphy_tx_power_ctl_setup()
4194 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR, in b43_nphy_tx_power_ctl_setup()
4203 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1))) in b43_nphy_tx_power_ctl_setup()
4207 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); in b43_nphy_tx_power_ctl_setup()
4210 b43_nphy_tx_prepare_adjusted_power_table(dev); in b43_nphy_tx_power_ctl_setup()
4211 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); in b43_nphy_tx_power_ctl_setup()
4212 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); in b43_nphy_tx_power_ctl_setup()
4215 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_tx_power_ctl_setup()
4218 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) in b43_nphy_tx_gain_table_upload() argument
4220 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_gain_table_upload()
4228 table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_tx_gain_table_upload()
4232 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); in b43_nphy_tx_gain_table_upload()
4233 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); in b43_nphy_tx_gain_table_upload()
4245 rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev); in b43_nphy_tx_gain_table_upload()
4259 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_tx_gain_table_upload()
4265 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_tx_gain_table_upload()
4271 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset); in b43_nphy_tx_gain_table_upload()
4272 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset); in b43_nphy_tx_gain_table_upload()
4277 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) in b43_nphy_pa_override() argument
4279 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_pa_override()
4284 nphy->rfctrl_intc1_save = b43_phy_read(dev, in b43_nphy_pa_override()
4286 nphy->rfctrl_intc2_save = b43_phy_read(dev, in b43_nphy_pa_override()
4288 band = b43_current_band(dev->wl); in b43_nphy_pa_override()
4289 if (dev->phy.rev >= 7) { in b43_nphy_pa_override()
4291 } else if (dev->phy.rev >= 3) { in b43_nphy_pa_override()
4302 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); in b43_nphy_pa_override()
4303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); in b43_nphy_pa_override()
4305 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, in b43_nphy_pa_override()
4307 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, in b43_nphy_pa_override()
4316 static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev) in b43_nphy_tx_lpf_bw() argument
4320 if (dev->phy.rev < 3 || dev->phy.rev >= 7) in b43_nphy_tx_lpf_bw()
4323 if (b43_nphy_ipa(dev)) in b43_nphy_tx_lpf_bw()
4324 tmp = b43_is_40mhz(dev) ? 5 : 4; in b43_nphy_tx_lpf_bw()
4326 tmp = b43_is_40mhz(dev) ? 3 : 1; in b43_nphy_tx_lpf_bw()
4327 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, in b43_nphy_tx_lpf_bw()
4330 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_lpf_bw()
4331 tmp = b43_is_40mhz(dev) ? 4 : 1; in b43_nphy_tx_lpf_bw()
4332 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, in b43_nphy_tx_lpf_bw()
4338 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, in b43_nphy_rx_iq_est() argument
4344 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); in b43_nphy_rx_iq_est()
4345 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); in b43_nphy_rx_iq_est()
4347 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); in b43_nphy_rx_iq_est()
4349 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); in b43_nphy_rx_iq_est()
4351 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); in b43_nphy_rx_iq_est()
4354 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); in b43_nphy_rx_iq_est()
4356 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4357 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); in b43_nphy_rx_iq_est()
4358 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4359 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); in b43_nphy_rx_iq_est()
4360 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4361 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); in b43_nphy_rx_iq_est()
4363 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4364 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); in b43_nphy_rx_iq_est()
4365 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4366 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); in b43_nphy_rx_iq_est()
4367 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4368 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); in b43_nphy_rx_iq_est()
4377 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, in b43_nphy_rx_iq_coeffs() argument
4381 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); in b43_nphy_rx_iq_coeffs()
4382 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); in b43_nphy_rx_iq_coeffs()
4383 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); in b43_nphy_rx_iq_coeffs()
4384 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); in b43_nphy_rx_iq_coeffs()
4386 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); in b43_nphy_rx_iq_coeffs()
4387 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); in b43_nphy_rx_iq_coeffs()
4388 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); in b43_nphy_rx_iq_coeffs()
4389 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); in b43_nphy_rx_iq_coeffs()
4396 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4398 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4400 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4402 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4403 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4405 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4406 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4408 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4409 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4410 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4411 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4412 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4413 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4414 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4415 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4419 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4422 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4424 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4426 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4427 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4429 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4430 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4432 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4433 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4434 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4435 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4436 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4437 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4438 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4439 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4441 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4442 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4444 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4447 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4449 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4451 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4455 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4456 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4458 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4459 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4462 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4463 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4464 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4473 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4475 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4481 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) in b43_nphy_calc_rx_iq_comp() argument
4499 b43_nphy_rx_iq_coeffs(dev, false, &old); in b43_nphy_calc_rx_iq_comp()
4500 b43_nphy_rx_iq_coeffs(dev, true, &new); in b43_nphy_calc_rx_iq_comp()
4501 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); in b43_nphy_calc_rx_iq_comp()
4554 if (dev->phy.rev >= 3) { in b43_nphy_calc_rx_iq_comp()
4562 if (dev->phy.rev >= 3) { in b43_nphy_calc_rx_iq_comp()
4575 b43_nphy_rx_iq_coeffs(dev, true, &new); in b43_nphy_calc_rx_iq_comp()
4579 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) in b43_nphy_tx_iq_workaround() argument
4582 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); in b43_nphy_tx_iq_workaround()
4584 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); in b43_nphy_tx_iq_workaround()
4585 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); in b43_nphy_tx_iq_workaround()
4586 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); in b43_nphy_tx_iq_workaround()
4587 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); in b43_nphy_tx_iq_workaround()
4591 static void b43_nphy_spur_workaround(struct b43_wldev *dev) in b43_nphy_spur_workaround() argument
4593 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_spur_workaround()
4595 u8 channel = dev->phy.channel; in b43_nphy_spur_workaround()
4599 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_spur_workaround()
4602 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_spur_workaround()
4606 if (channel == 11 && b43_is_40mhz(dev)) { in b43_nphy_spur_workaround()
4648 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_spur_workaround()
4652 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) in b43_nphy_tx_pwr_ctrl_coef_setup() argument
4654 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_pwr_ctrl_coef_setup()
4662 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_tx_pwr_ctrl_coef_setup()
4664 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); in b43_nphy_tx_pwr_ctrl_coef_setup()
4669 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_tx_pwr_ctrl_coef_setup()
4672 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, in b43_nphy_tx_pwr_ctrl_coef_setup()
4674 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_tx_pwr_ctrl_coef_setup()
4683 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_tx_pwr_ctrl_coef_setup()
4686 if (dev->phy.rev >= 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4693 if (dev->phy.rev < 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4699 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, in b43_nphy_tx_pwr_ctrl_coef_setup()
4701 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_tx_pwr_ctrl_coef_setup()
4706 if (dev->phy.rev >= 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4707 b43_shm_write16(dev, B43_SHM_SHARED, in b43_nphy_tx_pwr_ctrl_coef_setup()
4709 b43_shm_write16(dev, B43_SHM_SHARED, in b43_nphy_tx_pwr_ctrl_coef_setup()
4714 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_tx_pwr_ctrl_coef_setup()
4721 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) in b43_nphy_restore_rssi_cal() argument
4723 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_restore_rssi_cal()
4728 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_restore_rssi_cal()
4740 if (dev->phy.rev >= 19) { in b43_nphy_restore_rssi_cal()
4742 } else if (dev->phy.rev >= 7) { in b43_nphy_restore_rssi_cal()
4743 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, in b43_nphy_restore_rssi_cal()
4745 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, in b43_nphy_restore_rssi_cal()
4748 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4750 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4754 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); in b43_nphy_restore_rssi_cal()
4755 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); in b43_nphy_restore_rssi_cal()
4756 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); in b43_nphy_restore_rssi_cal()
4757 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); in b43_nphy_restore_rssi_cal()
4759 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); in b43_nphy_restore_rssi_cal()
4760 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); in b43_nphy_restore_rssi_cal()
4761 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); in b43_nphy_restore_rssi_cal()
4762 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); in b43_nphy_restore_rssi_cal()
4764 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); in b43_nphy_restore_rssi_cal()
4765 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); in b43_nphy_restore_rssi_cal()
4766 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); in b43_nphy_restore_rssi_cal()
4767 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); in b43_nphy_restore_rssi_cal()
4770 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup_rev19() argument
4775 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup_rev7() argument
4777 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_radio_setup_rev7()
4778 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_radio_setup_rev7()
4787 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); in b43_nphy_tx_cal_radio_setup_rev7()
4788 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); in b43_nphy_tx_cal_radio_setup_rev7()
4789 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); in b43_nphy_tx_cal_radio_setup_rev7()
4790 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); in b43_nphy_tx_cal_radio_setup_rev7()
4792 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); in b43_nphy_tx_cal_radio_setup_rev7()
4794 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); in b43_nphy_tx_cal_radio_setup_rev7()
4795 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); in b43_nphy_tx_cal_radio_setup_rev7()
4796 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); in b43_nphy_tx_cal_radio_setup_rev7()
4798 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_tx_cal_radio_setup_rev7()
4799 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); in b43_nphy_tx_cal_radio_setup_rev7()
4800 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4801 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4802 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4803 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4805 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); in b43_nphy_tx_cal_radio_setup_rev7()
4807 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); in b43_nphy_tx_cal_radio_setup_rev7()
4809 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); in b43_nphy_tx_cal_radio_setup_rev7()
4811 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4812 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4813 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4814 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4817 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4819 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4821 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); in b43_nphy_tx_cal_radio_setup_rev7()
4823 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4829 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup() argument
4831 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_radio_setup()
4832 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_radio_setup()
4838 b43_nphy_tx_cal_radio_setup_rev19(dev); in b43_nphy_tx_cal_radio_setup()
4840 b43_nphy_tx_cal_radio_setup_rev7(dev); in b43_nphy_tx_cal_radio_setup()
4846 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); in b43_nphy_tx_cal_radio_setup()
4847 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL); in b43_nphy_tx_cal_radio_setup()
4848 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS); in b43_nphy_tx_cal_radio_setup()
4849 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS); in b43_nphy_tx_cal_radio_setup()
4850 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS); in b43_nphy_tx_cal_radio_setup()
4851 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV); in b43_nphy_tx_cal_radio_setup()
4852 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1); in b43_nphy_tx_cal_radio_setup()
4853 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2); in b43_nphy_tx_cal_radio_setup()
4854 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL); in b43_nphy_tx_cal_radio_setup()
4855 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC); in b43_nphy_tx_cal_radio_setup()
4856 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1); in b43_nphy_tx_cal_radio_setup()
4858 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_tx_cal_radio_setup()
4859 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); in b43_nphy_tx_cal_radio_setup()
4860 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4861 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4862 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4863 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4865 b43_radio_write(dev, tmp | B2055_PADDRV, 4); in b43_nphy_tx_cal_radio_setup()
4866 b43_radio_write(dev, tmp | B2055_XOCTL1, 1); in b43_nphy_tx_cal_radio_setup()
4868 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4869 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); in b43_nphy_tx_cal_radio_setup()
4871 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4873 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); in b43_nphy_tx_cal_radio_setup()
4874 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4875 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4876 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4877 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4878 b43_radio_write(dev, tmp | B2055_XOCTL1, 0); in b43_nphy_tx_cal_radio_setup()
4880 b43_radio_write(dev, tmp | B2055_PADDRV, 6); in b43_nphy_tx_cal_radio_setup()
4881 b43_radio_write(dev, tmp | B2055_XOCTL2, in b43_nphy_tx_cal_radio_setup()
4882 (dev->phy.rev < 5) ? 0x11 : 0x01); in b43_nphy_tx_cal_radio_setup()
4884 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4885 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4888 b43_radio_write(dev, tmp | B2055_XOREGUL, 0); in b43_nphy_tx_cal_radio_setup()
4889 b43_radio_write(dev, tmp | B2055_XOMISC, 0); in b43_nphy_tx_cal_radio_setup()
4890 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); in b43_nphy_tx_cal_radio_setup()
4893 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4894 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4896 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2); in b43_nphy_tx_cal_radio_setup()
4897 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4899 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4900 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4902 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2); in b43_nphy_tx_cal_radio_setup()
4903 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4905 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX); in b43_nphy_tx_cal_radio_setup()
4906 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX); in b43_nphy_tx_cal_radio_setup()
4908 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & in b43_nphy_tx_cal_radio_setup()
4910 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4911 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4913 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4914 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4917 if (dev->phy.rev < 2) { in b43_nphy_tx_cal_radio_setup()
4918 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4919 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4921 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4922 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4928 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) in b43_nphy_update_tx_cal_ladder() argument
4930 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_update_tx_cal_ladder()
4942 b43_ntab_write(dev, B43_NTAB16(15, i), entry); in b43_nphy_update_tx_cal_ladder()
4946 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); in b43_nphy_update_tx_cal_ladder()
4950 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset, in b43_nphy_pa_set_tx_dig_filter() argument
4958 b43_phy_write(dev, offset, filter[i]); in b43_nphy_pa_set_tx_dig_filter()
4962 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) in b43_nphy_ext_pa_set_tx_dig_filters() argument
4964 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, in b43_nphy_ext_pa_set_tx_dig_filters()
4969 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) in b43_nphy_int_pa_set_tx_dig_filters() argument
4981 b43_nphy_pa_set_tx_dig_filter(dev, offset[i], in b43_nphy_int_pa_set_tx_dig_filters()
4985 if (dev->phy.rev == 16) in b43_nphy_int_pa_set_tx_dig_filters()
4986 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4989 if (dev->phy.rev == 17) { in b43_nphy_int_pa_set_tx_dig_filters()
4990 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4991 b43_nphy_pa_set_tx_dig_filter(dev, 0x195, in b43_nphy_int_pa_set_tx_dig_filters()
4995 if (b43_is_40mhz(dev)) { in b43_nphy_int_pa_set_tx_dig_filters()
4996 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4999 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_int_pa_set_tx_dig_filters()
5000 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
5002 if (dev->phy.channel == 14) in b43_nphy_int_pa_set_tx_dig_filters()
5003 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
5009 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) in b43_nphy_get_tx_gains() argument
5011 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_get_tx_gains()
5021 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_get_tx_gains()
5022 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); in b43_nphy_get_tx_gains()
5024 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_get_tx_gains()
5027 if (dev->phy.rev >= 7) { in b43_nphy_get_tx_gains()
5033 } else if (dev->phy.rev >= 3) { in b43_nphy_get_tx_gains()
5048 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5051 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5056 table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_get_tx_gains()
5060 if (dev->phy.rev >= 7) { in b43_nphy_get_tx_gains()
5066 } else if (dev->phy.rev >= 3) { in b43_nphy_get_tx_gains()
5084 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) in b43_nphy_tx_cal_phy_cleanup() argument
5086 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; in b43_nphy_tx_cal_phy_cleanup()
5088 if (dev->phy.rev >= 3) { in b43_nphy_tx_cal_phy_cleanup()
5089 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5090 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5091 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); in b43_nphy_tx_cal_phy_cleanup()
5092 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); in b43_nphy_tx_cal_phy_cleanup()
5093 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); in b43_nphy_tx_cal_phy_cleanup()
5094 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); in b43_nphy_tx_cal_phy_cleanup()
5095 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); in b43_nphy_tx_cal_phy_cleanup()
5096 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); in b43_nphy_tx_cal_phy_cleanup()
5097 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); in b43_nphy_tx_cal_phy_cleanup()
5098 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); in b43_nphy_tx_cal_phy_cleanup()
5099 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); in b43_nphy_tx_cal_phy_cleanup()
5100 b43_nphy_reset_cca(dev); in b43_nphy_tx_cal_phy_cleanup()
5102 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5103 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5104 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); in b43_nphy_tx_cal_phy_cleanup()
5105 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); in b43_nphy_tx_cal_phy_cleanup()
5106 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); in b43_nphy_tx_cal_phy_cleanup()
5107 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); in b43_nphy_tx_cal_phy_cleanup()
5108 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); in b43_nphy_tx_cal_phy_cleanup()
5113 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) in b43_nphy_tx_cal_phy_setup() argument
5115 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_phy_setup()
5116 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_phy_setup()
5117 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; in b43_nphy_tx_cal_phy_setup()
5120 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_tx_cal_phy_setup()
5121 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_tx_cal_phy_setup()
5122 if (dev->phy.rev >= 3) { in b43_nphy_tx_cal_phy_setup()
5123 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5124 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5126 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); in b43_nphy_tx_cal_phy_setup()
5128 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5130 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_tx_cal_phy_setup()
5132 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5134 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_nphy_tx_cal_phy_setup()
5135 b43_phy_mask(dev, B43_NPHY_BBCFG, in b43_nphy_tx_cal_phy_setup()
5138 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); in b43_nphy_tx_cal_phy_setup()
5140 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); in b43_nphy_tx_cal_phy_setup()
5142 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); in b43_nphy_tx_cal_phy_setup()
5144 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); in b43_nphy_tx_cal_phy_setup()
5145 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_tx_cal_phy_setup()
5146 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_tx_cal_phy_setup()
5149 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, in b43_nphy_tx_cal_phy_setup()
5152 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, in b43_nphy_tx_cal_phy_setup()
5154 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); in b43_nphy_tx_cal_phy_setup()
5155 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); in b43_nphy_tx_cal_phy_setup()
5157 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); in b43_nphy_tx_cal_phy_setup()
5158 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); in b43_nphy_tx_cal_phy_setup()
5159 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5160 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5162 tmp = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_tx_cal_phy_setup()
5164 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5167 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5172 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5175 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5178 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); in b43_nphy_tx_cal_phy_setup()
5179 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_tx_cal_phy_setup()
5180 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5181 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5183 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5184 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5189 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5190 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5191 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_tx_cal_phy_setup()
5193 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); in b43_nphy_tx_cal_phy_setup()
5194 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); in b43_nphy_tx_cal_phy_setup()
5197 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); in b43_nphy_tx_cal_phy_setup()
5198 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); in b43_nphy_tx_cal_phy_setup()
5201 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); in b43_nphy_tx_cal_phy_setup()
5202 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_tx_cal_phy_setup()
5203 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_tx_cal_phy_setup()
5204 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_tx_cal_phy_setup()
5208 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); in b43_nphy_tx_cal_phy_setup()
5209 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); in b43_nphy_tx_cal_phy_setup()
5214 static void b43_nphy_save_cal(struct b43_wldev *dev) in b43_nphy_save_cal() argument
5216 struct b43_phy *phy = &dev->phy; in b43_nphy_save_cal()
5217 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_save_cal()
5225 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_save_cal()
5227 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_save_cal()
5239 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); in b43_nphy_save_cal()
5244 txcal_radio_regs[0] = b43_radio_read(dev, in b43_nphy_save_cal()
5246 txcal_radio_regs[1] = b43_radio_read(dev, in b43_nphy_save_cal()
5248 txcal_radio_regs[4] = b43_radio_read(dev, in b43_nphy_save_cal()
5250 txcal_radio_regs[5] = b43_radio_read(dev, in b43_nphy_save_cal()
5252 txcal_radio_regs[2] = b43_radio_read(dev, in b43_nphy_save_cal()
5254 txcal_radio_regs[3] = b43_radio_read(dev, in b43_nphy_save_cal()
5256 txcal_radio_regs[6] = b43_radio_read(dev, in b43_nphy_save_cal()
5258 txcal_radio_regs[7] = b43_radio_read(dev, in b43_nphy_save_cal()
5261 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); in b43_nphy_save_cal()
5262 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); in b43_nphy_save_cal()
5263 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); in b43_nphy_save_cal()
5264 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); in b43_nphy_save_cal()
5265 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); in b43_nphy_save_cal()
5266 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); in b43_nphy_save_cal()
5267 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); in b43_nphy_save_cal()
5268 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); in b43_nphy_save_cal()
5270 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); in b43_nphy_save_cal()
5271 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); in b43_nphy_save_cal()
5272 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); in b43_nphy_save_cal()
5273 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); in b43_nphy_save_cal()
5275 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq; in b43_nphy_save_cal()
5277 cfg80211_get_chandef_type(dev->phy.chandef); in b43_nphy_save_cal()
5278 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); in b43_nphy_save_cal()
5281 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_save_cal()
5285 static void b43_nphy_restore_cal(struct b43_wldev *dev) in b43_nphy_restore_cal() argument
5287 struct b43_phy *phy = &dev->phy; in b43_nphy_restore_cal()
5288 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_restore_cal()
5298 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_restore_cal()
5310 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); in b43_nphy_restore_cal()
5313 if (dev->phy.rev >= 3) in b43_nphy_restore_cal()
5319 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); in b43_nphy_restore_cal()
5320 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); in b43_nphy_restore_cal()
5321 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); in b43_nphy_restore_cal()
5323 if (dev->phy.rev < 2) in b43_nphy_restore_cal()
5324 b43_nphy_tx_iq_workaround(dev); in b43_nphy_restore_cal()
5326 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_restore_cal()
5338 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, in b43_nphy_restore_cal()
5340 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, in b43_nphy_restore_cal()
5342 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, in b43_nphy_restore_cal()
5344 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, in b43_nphy_restore_cal()
5346 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, in b43_nphy_restore_cal()
5348 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, in b43_nphy_restore_cal()
5350 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, in b43_nphy_restore_cal()
5352 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, in b43_nphy_restore_cal()
5355 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5356 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5357 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5358 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5359 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); in b43_nphy_restore_cal()
5360 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); in b43_nphy_restore_cal()
5361 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); in b43_nphy_restore_cal()
5362 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); in b43_nphy_restore_cal()
5364 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5365 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5366 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5367 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5369 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); in b43_nphy_restore_cal()
5373 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, in b43_nphy_cal_tx_iq_lo() argument
5377 struct b43_phy *phy = &dev->phy; in b43_nphy_cal_tx_iq_lo()
5378 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_cal_tx_iq_lo()
5395 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_cal_tx_iq_lo()
5397 if (dev->phy.rev >= 4) { in b43_nphy_cal_tx_iq_lo()
5402 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5405 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); in b43_nphy_cal_tx_iq_lo()
5409 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); in b43_nphy_cal_tx_iq_lo()
5411 b43_nphy_tx_cal_radio_setup(dev); in b43_nphy_cal_tx_iq_lo()
5412 b43_nphy_tx_cal_phy_setup(dev); in b43_nphy_cal_tx_iq_lo()
5414 phy6or5x = dev->phy.rev >= 6 || in b43_nphy_cal_tx_iq_lo()
5415 (dev->phy.rev == 5 && nphy->ipa2g_on && in b43_nphy_cal_tx_iq_lo()
5416 b43_current_band(dev->wl) == NL80211_BAND_2GHZ); in b43_nphy_cal_tx_iq_lo()
5418 if (b43_is_40mhz(dev)) { in b43_nphy_cal_tx_iq_lo()
5419 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5421 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, in b43_nphy_cal_tx_iq_lo()
5424 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5426 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, in b43_nphy_cal_tx_iq_lo()
5434 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); in b43_nphy_cal_tx_iq_lo()
5436 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); in b43_nphy_cal_tx_iq_lo()
5439 if (!b43_is_40mhz(dev)) in b43_nphy_cal_tx_iq_lo()
5445 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8, in b43_nphy_cal_tx_iq_lo()
5448 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false); in b43_nphy_cal_tx_iq_lo()
5454 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5460 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5464 if (dev->phy.rev >= 3) { in b43_nphy_cal_tx_iq_lo()
5474 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); in b43_nphy_cal_tx_iq_lo()
5477 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5482 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5499 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5504 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5514 b43_nphy_update_tx_cal_ladder(dev, core); in b43_nphy_cal_tx_iq_lo()
5519 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); in b43_nphy_cal_tx_iq_lo()
5522 buffer[0] = b43_ntab_read(dev, in b43_nphy_cal_tx_iq_lo()
5526 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), in b43_nphy_cal_tx_iq_lo()
5530 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); in b43_nphy_cal_tx_iq_lo()
5532 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); in b43_nphy_cal_tx_iq_lo()
5538 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5540 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, in b43_nphy_cal_tx_iq_lo()
5550 last = (dev->phy.rev < 3) ? 6 : 7; in b43_nphy_cal_tx_iq_lo()
5553 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); in b43_nphy_cal_tx_iq_lo()
5554 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); in b43_nphy_cal_tx_iq_lo()
5555 if (dev->phy.rev < 3) { in b43_nphy_cal_tx_iq_lo()
5561 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, in b43_nphy_cal_tx_iq_lo()
5563 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, in b43_nphy_cal_tx_iq_lo()
5565 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, in b43_nphy_cal_tx_iq_lo()
5567 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, in b43_nphy_cal_tx_iq_lo()
5570 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5572 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5581 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5583 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5587 b43_nphy_stop_playback(dev); in b43_nphy_cal_tx_iq_lo()
5588 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); in b43_nphy_cal_tx_iq_lo()
5591 b43_nphy_tx_cal_phy_cleanup(dev); in b43_nphy_cal_tx_iq_lo()
5592 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5594 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) in b43_nphy_cal_tx_iq_lo()
5595 b43_nphy_tx_iq_workaround(dev); in b43_nphy_cal_tx_iq_lo()
5597 if (dev->phy.rev >= 4) in b43_nphy_cal_tx_iq_lo()
5600 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_cal_tx_iq_lo()
5606 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) in b43_nphy_reapply_tx_cal_coeffs() argument
5608 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_reapply_tx_cal_coeffs()
5614 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq || in b43_nphy_reapply_tx_cal_coeffs()
5615 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef)) in b43_nphy_reapply_tx_cal_coeffs()
5618 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); in b43_nphy_reapply_tx_cal_coeffs()
5627 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, in b43_nphy_reapply_tx_cal_coeffs()
5631 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, in b43_nphy_reapply_tx_cal_coeffs()
5633 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, in b43_nphy_reapply_tx_cal_coeffs()
5635 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, in b43_nphy_reapply_tx_cal_coeffs()
5641 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_rev2_cal_rx_iq() argument
5644 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_rev2_cal_rx_iq()
5667 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_rev2_cal_rx_iq()
5669 if (dev->phy.rev < 2) in b43_nphy_rev2_cal_rx_iq()
5670 b43_nphy_reapply_tx_cal_coeffs(dev); in b43_nphy_rev2_cal_rx_iq()
5671 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5673 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); in b43_nphy_rev2_cal_rx_iq()
5676 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); in b43_nphy_rev2_cal_rx_iq()
5689 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); in b43_nphy_rev2_cal_rx_iq()
5690 tmp[2] = b43_phy_read(dev, afectl_core); in b43_nphy_rev2_cal_rx_iq()
5691 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_rev2_cal_rx_iq()
5692 tmp[4] = b43_phy_read(dev, rfctl[0]); in b43_nphy_rev2_cal_rx_iq()
5693 tmp[5] = b43_phy_read(dev, rfctl[1]); in b43_nphy_rev2_cal_rx_iq()
5695 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, in b43_nphy_rev2_cal_rx_iq()
5698 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, in b43_nphy_rev2_cal_rx_iq()
5700 b43_phy_set(dev, afectl_core, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5701 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5703 band = b43_current_band(dev->wl); in b43_nphy_rev2_cal_rx_iq()
5707 b43_phy_write(dev, rfctl[0], 0x140); in b43_nphy_rev2_cal_rx_iq()
5709 b43_phy_write(dev, rfctl[0], 0x110); in b43_nphy_rev2_cal_rx_iq()
5712 b43_phy_write(dev, rfctl[0], 0x180); in b43_nphy_rev2_cal_rx_iq()
5714 b43_phy_write(dev, rfctl[0], 0x120); in b43_nphy_rev2_cal_rx_iq()
5718 b43_phy_write(dev, rfctl[1], 0x148); in b43_nphy_rev2_cal_rx_iq()
5720 b43_phy_write(dev, rfctl[1], 0x114); in b43_nphy_rev2_cal_rx_iq()
5723 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5725 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5763 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, in b43_nphy_rev2_cal_rx_iq()
5765 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev2_cal_rx_iq()
5766 b43_nphy_stop_playback(dev); in b43_nphy_rev2_cal_rx_iq()
5769 ret = b43_nphy_tx_tone(dev, 4000, in b43_nphy_rev2_cal_rx_iq()
5774 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, in b43_nphy_rev2_cal_rx_iq()
5780 b43_nphy_rx_iq_est(dev, &est, 1024, 32, in b43_nphy_rev2_cal_rx_iq()
5791 b43_nphy_calc_rx_iq_comp(dev, 1 << i); in b43_nphy_rev2_cal_rx_iq()
5793 b43_nphy_stop_playback(dev); in b43_nphy_rev2_cal_rx_iq()
5800 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5801 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5802 b43_phy_write(dev, rfctl[1], tmp[5]); in b43_nphy_rev2_cal_rx_iq()
5803 b43_phy_write(dev, rfctl[0], tmp[4]); in b43_nphy_rev2_cal_rx_iq()
5804 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); in b43_nphy_rev2_cal_rx_iq()
5805 b43_phy_write(dev, afectl_core, tmp[2]); in b43_nphy_rev2_cal_rx_iq()
5806 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); in b43_nphy_rev2_cal_rx_iq()
5812 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); in b43_nphy_rev2_cal_rx_iq()
5813 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev2_cal_rx_iq()
5814 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5816 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_rev2_cal_rx_iq()
5821 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_rev3_cal_rx_iq() argument
5828 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_cal_rx_iq() argument
5831 if (dev->phy.rev >= 7) in b43_nphy_cal_rx_iq()
5834 if (dev->phy.rev >= 3) in b43_nphy_cal_rx_iq()
5835 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); in b43_nphy_cal_rx_iq()
5837 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); in b43_nphy_cal_rx_iq()
5841 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) in b43_nphy_set_rx_core_state() argument
5843 struct b43_phy *phy = &dev->phy; in b43_nphy_set_rx_core_state()
5852 b43_mac_suspend(dev); in b43_nphy_set_rx_core_state()
5855 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_set_rx_core_state()
5857 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, in b43_nphy_set_rx_core_state()
5861 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); in b43_nphy_set_rx_core_state()
5862 if (dev->phy.rev >= 3) { in b43_nphy_set_rx_core_state()
5866 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); in b43_nphy_set_rx_core_state()
5867 if (dev->phy.rev >= 3) { in b43_nphy_set_rx_core_state()
5872 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_set_rx_core_state()
5875 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_set_rx_core_state()
5877 b43_mac_enable(dev); in b43_nphy_set_rx_core_state()
5880 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, in b43_nphy_op_recalc_txpower() argument
5883 struct b43_phy *phy = &dev->phy; in b43_nphy_op_recalc_txpower()
5884 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_op_recalc_txpower()
5885 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; in b43_nphy_op_recalc_txpower()
5894 b43_ppr_clear(dev, ppr); in b43_nphy_op_recalc_txpower()
5897 b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G); in b43_nphy_op_recalc_txpower()
5903 b43_ppr_apply_max(dev, ppr, max); in b43_nphy_op_recalc_txpower()
5904 if (b43_debug(dev, B43_DBG_XMITPOWER)) in b43_nphy_op_recalc_txpower()
5905 b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n", in b43_nphy_op_recalc_txpower()
5906 Q52_ARG(b43_ppr_get_max(dev, ppr))); in b43_nphy_op_recalc_txpower()
5912 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_op_recalc_txpower()
5916 b43_ppr_add(dev, ppr, -hw_gain); in b43_nphy_op_recalc_txpower()
5920 b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8)); in b43_nphy_op_recalc_txpower()
5923 b43_mac_suspend(dev); in b43_nphy_op_recalc_txpower()
5924 b43_nphy_tx_power_ctl_setup(dev); in b43_nphy_op_recalc_txpower()
5925 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_op_recalc_txpower()
5926 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); in b43_nphy_op_recalc_txpower()
5927 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_op_recalc_txpower()
5930 b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl); in b43_nphy_op_recalc_txpower()
5931 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_op_recalc_txpower()
5932 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); in b43_nphy_op_recalc_txpower()
5933 b43_mac_enable(dev); in b43_nphy_op_recalc_txpower()
5946 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) in b43_nphy_update_mimo_config() argument
5948 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); in b43_nphy_update_mimo_config()
5956 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); in b43_nphy_update_mimo_config()
5960 static void b43_nphy_bphy_init(struct b43_wldev *dev) in b43_nphy_bphy_init() argument
5967 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); in b43_nphy_bphy_init()
5972 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); in b43_nphy_bphy_init()
5975 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); in b43_nphy_bphy_init()
5979 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) in b43_nphy_superswitch_init() argument
5981 if (dev->phy.rev >= 7) in b43_nphy_superswitch_init()
5984 if (dev->phy.rev >= 3) { in b43_nphy_superswitch_init()
5988 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); in b43_nphy_superswitch_init()
5989 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); in b43_nphy_superswitch_init()
5990 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); in b43_nphy_superswitch_init()
5991 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); in b43_nphy_superswitch_init()
5994 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); in b43_nphy_superswitch_init()
5995 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); in b43_nphy_superswitch_init()
5997 switch (dev->dev->bus_type) { in b43_nphy_superswitch_init()
6000 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, in b43_nphy_superswitch_init()
6006 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco, in b43_nphy_superswitch_init()
6012 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); in b43_nphy_superswitch_init()
6013 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); in b43_nphy_superswitch_init()
6014 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), in b43_nphy_superswitch_init()
6018 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_superswitch_init()
6019 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_superswitch_init()
6020 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_superswitch_init()
6021 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_superswitch_init()
6027 static int b43_phy_initn(struct b43_wldev *dev) in b43_phy_initn() argument
6029 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_phy_initn()
6030 struct b43_phy *phy = &dev->phy; in b43_phy_initn()
6040 if ((dev->phy.rev >= 3) && in b43_phy_initn()
6042 (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) { in b43_phy_initn()
6043 switch (dev->dev->bus_type) { in b43_phy_initn()
6046 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc, in b43_phy_initn()
6052 chipco_set32(&dev->dev->sdev->bus->chipco, in b43_phy_initn()
6058 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || in b43_phy_initn()
6063 b43_nphy_tables_init(dev); in b43_phy_initn()
6068 if (dev->phy.rev >= 3) { in b43_phy_initn()
6069 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); in b43_phy_initn()
6070 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6072 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); in b43_phy_initn()
6073 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); in b43_phy_initn()
6074 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); in b43_phy_initn()
6075 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); in b43_phy_initn()
6081 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); in b43_phy_initn()
6082 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); in b43_phy_initn()
6084 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6086 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); in b43_phy_initn()
6087 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); in b43_phy_initn()
6088 if (dev->phy.rev < 6) { in b43_phy_initn()
6089 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); in b43_phy_initn()
6090 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); in b43_phy_initn()
6092 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, in b43_phy_initn()
6095 if (dev->phy.rev >= 3) in b43_phy_initn()
6096 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); in b43_phy_initn()
6097 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); in b43_phy_initn()
6099 if (dev->phy.rev <= 2) { in b43_phy_initn()
6100 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; in b43_phy_initn()
6101 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_phy_initn()
6105 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); in b43_phy_initn()
6106 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); in b43_phy_initn()
6109 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && in b43_phy_initn()
6110 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93)) in b43_phy_initn()
6111 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); in b43_phy_initn()
6113 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); in b43_phy_initn()
6114 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); in b43_phy_initn()
6115 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); in b43_phy_initn()
6116 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); in b43_phy_initn()
6119 b43_nphy_update_mimo_config(dev, nphy->preamble_override); in b43_phy_initn()
6121 b43_nphy_update_txrx_chain(dev); in b43_phy_initn()
6124 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); in b43_phy_initn()
6125 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); in b43_phy_initn()
6128 if (b43_nphy_ipa(dev)) { in b43_phy_initn()
6129 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); in b43_phy_initn()
6130 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, in b43_phy_initn()
6132 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); in b43_phy_initn()
6133 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, in b43_phy_initn()
6135 b43_nphy_int_pa_set_tx_dig_filters(dev); in b43_phy_initn()
6137 b43_nphy_ext_pa_set_tx_dig_filters(dev); in b43_phy_initn()
6140 b43_nphy_workarounds(dev); in b43_phy_initn()
6143 b43_phy_force_clock(dev, 1); in b43_phy_initn()
6144 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_phy_initn()
6145 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); in b43_phy_initn()
6146 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); in b43_phy_initn()
6147 b43_phy_force_clock(dev, 0); in b43_phy_initn()
6149 b43_mac_phy_clock_set(dev, true); in b43_phy_initn()
6152 b43_nphy_pa_override(dev, false); in b43_phy_initn()
6153 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); in b43_phy_initn()
6154 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_phy_initn()
6155 b43_nphy_pa_override(dev, true); in b43_phy_initn()
6158 b43_nphy_classifier(dev, 0, 0); in b43_phy_initn()
6159 b43_nphy_read_clip_detection(dev, clip); in b43_phy_initn()
6160 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_phy_initn()
6161 b43_nphy_bphy_init(dev); in b43_phy_initn()
6164 b43_nphy_tx_power_ctrl(dev, false); in b43_phy_initn()
6165 b43_nphy_tx_power_fix(dev); in b43_phy_initn()
6166 b43_nphy_tx_power_ctl_idle_tssi(dev); in b43_phy_initn()
6167 b43_nphy_tx_power_ctl_setup(dev); in b43_phy_initn()
6168 b43_nphy_tx_gain_table_upload(dev); in b43_phy_initn()
6171 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); in b43_phy_initn()
6178 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_phy_initn()
6184 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6186 b43_nphy_restore_rssi_cal(dev); in b43_phy_initn()
6188 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6192 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_phy_initn()
6201 target = b43_nphy_get_tx_gains(dev); in b43_phy_initn()
6204 b43_nphy_superswitch_init(dev, true); in b43_phy_initn()
6206 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6213 target = b43_nphy_get_tx_gains(dev); in b43_phy_initn()
6215 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) in b43_phy_initn()
6216 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) in b43_phy_initn()
6217 b43_nphy_save_cal(dev); in b43_phy_initn()
6222 b43_nphy_restore_cal(dev); in b43_phy_initn()
6226 b43_nphy_tx_pwr_ctrl_coef_setup(dev); in b43_phy_initn()
6227 b43_nphy_tx_power_ctrl(dev, tx_pwr_state); in b43_phy_initn()
6228 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); in b43_phy_initn()
6229 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); in b43_phy_initn()
6231 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); in b43_phy_initn()
6232 b43_nphy_tx_lpf_bw(dev); in b43_phy_initn()
6234 b43_nphy_spur_workaround(dev); in b43_phy_initn()
6243 static void b43_chantab_phy_upload(struct b43_wldev *dev, in b43_chantab_phy_upload() argument
6246 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); in b43_chantab_phy_upload()
6247 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); in b43_chantab_phy_upload()
6248 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); in b43_chantab_phy_upload()
6249 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); in b43_chantab_phy_upload()
6250 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); in b43_chantab_phy_upload()
6251 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); in b43_chantab_phy_upload()
6255 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) in b43_nphy_pmu_spur_avoid() argument
6257 switch (dev->dev->bus_type) { in b43_nphy_pmu_spur_avoid()
6260 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc, in b43_nphy_pmu_spur_avoid()
6266 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, in b43_nphy_pmu_spur_avoid()
6274 static void b43_nphy_channel_setup(struct b43_wldev *dev, in b43_nphy_channel_setup() argument
6278 struct b43_phy *phy = &dev->phy; in b43_nphy_channel_setup()
6279 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_channel_setup()
6285 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6287 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); in b43_nphy_channel_setup()
6288 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); in b43_nphy_channel_setup()
6290 b43_phy_set(dev, B43_PHY_B_BBCFG, in b43_nphy_channel_setup()
6292 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); in b43_nphy_channel_setup()
6293 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6295 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6296 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); in b43_nphy_channel_setup()
6297 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); in b43_nphy_channel_setup()
6299 b43_phy_mask(dev, B43_PHY_B_BBCFG, in b43_nphy_channel_setup()
6301 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); in b43_nphy_channel_setup()
6304 b43_chantab_phy_upload(dev, e); in b43_nphy_channel_setup()
6307 b43_nphy_classifier(dev, 2, 0); in b43_nphy_channel_setup()
6308 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); in b43_nphy_channel_setup()
6310 b43_nphy_classifier(dev, 2, 2); in b43_nphy_channel_setup()
6312 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); in b43_nphy_channel_setup()
6316 b43_nphy_tx_power_fix(dev); in b43_nphy_channel_setup()
6318 if (dev->phy.rev < 3) in b43_nphy_channel_setup()
6319 b43_nphy_adjust_lna_gain_table(dev); in b43_nphy_channel_setup()
6321 b43_nphy_tx_lpf_bw(dev); in b43_nphy_channel_setup()
6323 if (dev->phy.rev >= 3 && in b43_nphy_channel_setup()
6324 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) { in b43_nphy_channel_setup()
6327 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) { in b43_nphy_channel_setup()
6338 if (!b43_is_40mhz(dev)) { /* 20MHz */ in b43_nphy_channel_setup()
6346 if (!b43_is_40mhz(dev)) { /* 20MHz */ in b43_nphy_channel_setup()
6352 spuravoid = dev->dev->chip_id == 0x4716; in b43_nphy_channel_setup()
6356 b43_nphy_pmu_spur_avoid(dev, spuravoid); in b43_nphy_channel_setup()
6358 b43_mac_switch_freq(dev, spuravoid); in b43_nphy_channel_setup()
6360 if (dev->phy.rev == 3 || dev->phy.rev == 4) in b43_nphy_channel_setup()
6361 b43_wireless_core_phy_pll_reset(dev); in b43_nphy_channel_setup()
6364 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX); in b43_nphy_channel_setup()
6366 b43_phy_mask(dev, B43_NPHY_BBCFG, in b43_nphy_channel_setup()
6369 b43_nphy_reset_cca(dev); in b43_nphy_channel_setup()
6374 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); in b43_nphy_channel_setup()
6377 b43_nphy_spur_workaround(dev); in b43_nphy_channel_setup()
6381 static int b43_nphy_set_channel(struct b43_wldev *dev, in b43_nphy_set_channel() argument
6385 struct b43_phy *phy = &dev->phy; in b43_nphy_set_channel()
6398 r2057_get_chantabent_rev7(dev, channel->center_freq, in b43_nphy_set_channel()
6403 tabent_r3 = b43_nphy_get_chantabent_rev3(dev, in b43_nphy_set_channel()
6408 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, in b43_nphy_set_channel()
6425 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20); in b43_nphy_set_channel()
6427 b43_phy_set(dev, 0x310, 0x8000); in b43_nphy_set_channel()
6429 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20); in b43_nphy_set_channel()
6431 b43_phy_mask(dev, 0x310, (u16)~0x8000); in b43_nphy_set_channel()
6442 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp); in b43_nphy_set_channel()
6443 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp); in b43_nphy_set_channel()
6446 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g); in b43_nphy_set_channel()
6447 b43_nphy_channel_setup(dev, phy_regs, channel); in b43_nphy_set_channel()
6450 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); in b43_nphy_set_channel()
6451 b43_radio_2056_setup(dev, tabent_r3); in b43_nphy_set_channel()
6452 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); in b43_nphy_set_channel()
6455 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); in b43_nphy_set_channel()
6456 b43_radio_2055_setup(dev, tabent_r2); in b43_nphy_set_channel()
6457 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); in b43_nphy_set_channel()
6467 static int b43_nphy_op_allocate(struct b43_wldev *dev) in b43_nphy_op_allocate() argument
6475 dev->phy.n = nphy; in b43_nphy_op_allocate()
6480 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) in b43_nphy_op_prepare_structs() argument
6482 struct b43_phy *phy = &dev->phy; in b43_nphy_op_prepare_structs()
6484 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_op_prepare_structs()
6503 if (dev->phy.rev >= 3 || in b43_nphy_op_prepare_structs()
6504 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && in b43_nphy_op_prepare_structs()
6505 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) { in b43_nphy_op_prepare_structs()
6509 if (dev->phy.rev >= 2 && in b43_nphy_op_prepare_structs()
6513 if (dev->dev->bus_type == B43_BUS_SSB && in b43_nphy_op_prepare_structs()
6514 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { in b43_nphy_op_prepare_structs()
6516 dev->dev->sdev->bus->host_pci; in b43_nphy_op_prepare_structs()
6527 if (dev->phy.rev >= 3) { in b43_nphy_op_prepare_structs()
6533 static void b43_nphy_op_free(struct b43_wldev *dev) in b43_nphy_op_free() argument
6535 struct b43_phy *phy = &dev->phy; in b43_nphy_op_free()
6542 static int b43_nphy_op_init(struct b43_wldev *dev) in b43_nphy_op_init() argument
6544 return b43_phy_initn(dev); in b43_nphy_op_init()
6547 static inline void check_phyreg(struct b43_wldev *dev, u16 offset) in check_phyreg() argument
6552 b43err(dev->wl, "Invalid OFDM PHY access at " in check_phyreg()
6558 b43err(dev->wl, "Invalid EXT-G PHY access at " in check_phyreg()
6565 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, in b43_nphy_op_maskset() argument
6568 check_phyreg(dev, reg); in b43_nphy_op_maskset()
6569 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_nphy_op_maskset()
6570 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); in b43_nphy_op_maskset()
6571 dev->phy.writes_counter = 1; in b43_nphy_op_maskset()
6574 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_nphy_op_radio_read() argument
6577 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); in b43_nphy_op_radio_read()
6579 if (dev->phy.rev >= 7) in b43_nphy_op_radio_read()
6584 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_nphy_op_radio_read()
6585 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_nphy_op_radio_read()
6588 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_nphy_op_radio_write() argument
6591 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); in b43_nphy_op_radio_write()
6593 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_nphy_op_radio_write()
6594 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_nphy_op_radio_write()
6598 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, in b43_nphy_op_software_rfkill() argument
6601 struct b43_phy *phy = &dev->phy; in b43_nphy_op_software_rfkill()
6603 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) in b43_nphy_op_software_rfkill()
6604 b43err(dev->wl, "MAC not suspended\n"); in b43_nphy_op_software_rfkill()
6610 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_op_software_rfkill()
6615 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_op_software_rfkill()
6618 b43_radio_mask(dev, 0x09, ~0x2); in b43_nphy_op_software_rfkill()
6620 b43_radio_write(dev, 0x204D, 0); in b43_nphy_op_software_rfkill()
6621 b43_radio_write(dev, 0x2053, 0); in b43_nphy_op_software_rfkill()
6622 b43_radio_write(dev, 0x2058, 0); in b43_nphy_op_software_rfkill()
6623 b43_radio_write(dev, 0x205E, 0); in b43_nphy_op_software_rfkill()
6624 b43_radio_mask(dev, 0x2062, ~0xF0); in b43_nphy_op_software_rfkill()
6625 b43_radio_write(dev, 0x2064, 0); in b43_nphy_op_software_rfkill()
6627 b43_radio_write(dev, 0x304D, 0); in b43_nphy_op_software_rfkill()
6628 b43_radio_write(dev, 0x3053, 0); in b43_nphy_op_software_rfkill()
6629 b43_radio_write(dev, 0x3058, 0); in b43_nphy_op_software_rfkill()
6630 b43_radio_write(dev, 0x305E, 0); in b43_nphy_op_software_rfkill()
6631 b43_radio_mask(dev, 0x3062, ~0xF0); in b43_nphy_op_software_rfkill()
6632 b43_radio_write(dev, 0x3064, 0); in b43_nphy_op_software_rfkill()
6638 if (!dev->phy.radio_on) in b43_nphy_op_software_rfkill()
6639 b43_radio_2057_init(dev); in b43_nphy_op_software_rfkill()
6640 b43_switch_channel(dev, dev->phy.channel); in b43_nphy_op_software_rfkill()
6642 if (!dev->phy.radio_on) in b43_nphy_op_software_rfkill()
6643 b43_radio_init2056(dev); in b43_nphy_op_software_rfkill()
6644 b43_switch_channel(dev, dev->phy.channel); in b43_nphy_op_software_rfkill()
6646 b43_radio_init2055(dev); in b43_nphy_op_software_rfkill()
6652 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) in b43_nphy_op_switch_analog() argument
6654 struct b43_phy *phy = &dev->phy; in b43_nphy_op_switch_analog()
6662 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); in b43_nphy_op_switch_analog()
6663 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); in b43_nphy_op_switch_analog()
6664 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); in b43_nphy_op_switch_analog()
6665 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6667 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); in b43_nphy_op_switch_analog()
6668 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); in b43_nphy_op_switch_analog()
6669 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6670 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); in b43_nphy_op_switch_analog()
6673 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6677 static int b43_nphy_op_switch_channel(struct b43_wldev *dev, in b43_nphy_op_switch_channel() argument
6680 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; in b43_nphy_op_switch_channel()
6682 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); in b43_nphy_op_switch_channel()
6684 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_op_switch_channel()
6692 return b43_nphy_set_channel(dev, channel, channel_type); in b43_nphy_op_switch_channel()
6695 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) in b43_nphy_op_get_default_chan() argument
6697 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_op_get_default_chan()