Lines Matching +full:0 +full:x07000000
20 #define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
25 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
29 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
32 MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0),
50 #define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
51 #define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
52 #define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
53 #define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
54 #define MCI_BT_MCI_FLAGS_DEBUG 0x00000020
55 #define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
56 #define MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
57 #define MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
58 #define MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
59 #define MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
60 #define MCI_BT_MCI_FLAGS_AR9462_MODE 0x00001000
61 #define MCI_BT_MCI_FLAGS_OTHER 0x00010000
63 #define MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
70 #define MCI_2G_FLAGS_CLEAR_MASK 0x00000000
75 #define MCI_5G_FLAGS_SET_MASK 0x00000000
80 * Default value for AR9462 is 0x00002201
82 #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
83 #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
84 #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
85 #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
86 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
87 #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
88 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
89 #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
91 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
92 #define ATH_MCI_CONFIG_CLK_DIV 0x00003000
94 #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
95 #define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000
96 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000
98 #define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000
100 #define ATH_MCI_CONFIG_ANT_ARCH 0x07000000
102 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000
104 #define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000
105 #define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000
106 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
107 #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
113 #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
115 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
116 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
117 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
118 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
119 #define ATH_MCI_ANT_ARCH_3_ANT 0x04
126 MCI_LNA_CTRL = 0x10, /* len = 0 */
127 MCI_CONT_NACK = 0x20, /* len = 0 */
128 MCI_CONT_INFO = 0x30, /* len = 4 */
129 MCI_CONT_RST = 0x40, /* len = 0 */
130 MCI_SCHD_INFO = 0x50, /* len = 16 */
131 MCI_CPU_INT = 0x60, /* len = 4 */
132 MCI_SYS_WAKING = 0x70, /* len = 0 */
133 MCI_GPM = 0x80, /* len = 16 */
134 MCI_LNA_INFO = 0x90, /* len = 1 */
135 MCI_LNA_STATE = 0x94,
136 MCI_LNA_TAKE = 0x98,
137 MCI_LNA_TRANS = 0x9c,
138 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
139 MCI_REQ_WAKE = 0xc0, /* len = 0 */
140 MCI_DEBUG_16 = 0xfe, /* len = 2 */
141 MCI_REMOTE_RESET = 0xff /* len = 16 */
194 MCI_GPM_BT_CAL_REQ = 0,
200 MCI_GPM_COEX_AGENT = 0x0c,
201 MCI_GPM_RSVD_PATTERN = 0xfe,
202 MCI_GPM_RSVD_PATTERN32 = 0xfefefefe,
203 MCI_GPM_BT_DEBUG = 0xff
277 #define MCI_GPM_NOMORE 0
279 #define MCI_GPM_INVALID 0xffffffff
284 } while (0)
287 (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
290 (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
293 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
294 } while (0)
297 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
298 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
299 } while (0)
368 return 0; in ar9003_mci_end_reset()