31 #define AR5008_11NA_OFDM_SHIFT		0
55 	{0x000098b0, 0x1e5795e5},
56 	{0x000098e0, 0x02008020},
61 	{0x000098b0, 0x02108421},
62 	{0x000098ec, 0x00000008},
67 	{0x000098b0, 0x0e73ff17},
68 	{0x000098e0, 0x00000420},
73 	{0x000098f0, 0x01400018, 0x01c00018},
78 	{0x0000989c, 0x00000500},
79 	{0x0000989c, 0x00000800},
80 	{0x000098cc, 0x0000000e},
97 	for (r = 0; r < array->ia_rows; r++) {  in ar5008_write_bank6()
98 		REG_WRITE(ah, INI_RA(array, r, 0), data[r]);  in ar5008_write_bank6()
127 	while (bitsLeft > 0) {  in ar5008_hw_phy_modify_rx_buffer()
137 		bitPosition = 0;  in ar5008_hw_phy_modify_rx_buffer()
150  *            bias = 0
155  *      else if forceBias > 0
167  *    Less than 2412 uses value of 0, 2412 and above uses value of 2
173 	int reg_writes = 0;  in ar5008_hw_force_bias()
174 	u32 new_bias = 0;  in ar5008_hw_force_bias()
182 		new_bias = 0;  in ar5008_hw_force_bias()
213 	u32 channelSel = 0;  in ar5008_hw_set_channel()
214 	u32 bModeSynth = 0;  in ar5008_hw_set_channel()
215 	u32 aModeRefSel = 0;  in ar5008_hw_set_channel()
216 	u32 reg32 = 0;  in ar5008_hw_set_channel()
226 		if (((freq - 2192) % 5) == 0) {  in ar5008_hw_set_channel()
228 			bModeSynth = 0;  in ar5008_hw_set_channel()
229 		} else if (((freq - 2224) % 5) == 0) {  in ar5008_hw_set_channel()
237 		channelSel = (channelSel << 2) & 0xff;  in ar5008_hw_set_channel()
250 	} else if ((freq % 20) == 0 && freq >= 5120) {  in ar5008_hw_set_channel()
254 	} else if ((freq % 10) == 0) {  in ar5008_hw_set_channel()
261 	} else if ((freq % 5) == 0) {  in ar5008_hw_set_channel()
273 	    (1 << 5) | 0x1;  in ar5008_hw_set_channel()
275 	REG_WRITE(ah, AR_PHY(0x37), reg32);  in ar5008_hw_set_channel()
279 	return 0;  in ar5008_hw_set_channel()
288 	int8_t mask_m[123] = {0};  in ar5008_hw_cmn_spur_mitigate()
289 	int8_t mask_p[123] = {0};  in ar5008_hw_cmn_spur_mitigate()
300 	static const int inc[4] = { 0, 100, 0, 0 };  in ar5008_hw_cmn_spur_mitigate()
306 	for (i = 0; i < 4; i++) {  in ar5008_hw_cmn_spur_mitigate()
307 		int pilot_mask = 0;  in ar5008_hw_cmn_spur_mitigate()
308 		int chan_mask = 0;  in ar5008_hw_cmn_spur_mitigate()
309 		int bp = 0;  in ar5008_hw_cmn_spur_mitigate()
311 		for (bp = 0; bp < 30; bp++) {  in ar5008_hw_cmn_spur_mitigate()
313 				pilot_mask = pilot_mask | 0x1 << bp;  in ar5008_hw_cmn_spur_mitigate()
314 				chan_mask = chan_mask | 0x1 << bp;  in ar5008_hw_cmn_spur_mitigate()
327 	for (i = 0; i < ARRAY_SIZE(mask_m); i++) {  in ar5008_hw_cmn_spur_mitigate()
335 				mask_amt = 0;  in ar5008_hw_cmn_spur_mitigate()
336 			if (cur_vit_mask < 0)  in ar5008_hw_cmn_spur_mitigate()
351 		| (mask_m[60] << 2) | (mask_m[61] << 0);  in ar5008_hw_cmn_spur_mitigate()
362 		| (mask_m[44] << 2) | (mask_m[45] << 0);  in ar5008_hw_cmn_spur_mitigate()
373 		| (mask_m[29] << 2) | (mask_m[30] << 0);  in ar5008_hw_cmn_spur_mitigate()
377 	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)  in ar5008_hw_cmn_spur_mitigate()
384 		| (mask_m[14] << 2) | (mask_m[15] << 0);  in ar5008_hw_cmn_spur_mitigate()
395 		| (mask_p[2] << 2) | (mask_p[1] << 0);  in ar5008_hw_cmn_spur_mitigate()
406 		| (mask_p[17] << 2) | (mask_p[16] << 0);  in ar5008_hw_cmn_spur_mitigate()
417 		| (mask_p[32] << 2) | (mask_p[31] << 0);  in ar5008_hw_cmn_spur_mitigate()
428 		| (mask_p[47] << 2) | (mask_p[46] << 0);  in ar5008_hw_cmn_spur_mitigate()
455 	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {  in ar5008_hw_spur_mitigate()
471 	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));  in ar5008_hw_spur_mitigate()
477 	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);  in ar5008_hw_spur_mitigate()
490 	spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;  in ar5008_hw_spur_mitigate()
511 	    return 0;  in ar5008_hw_rf_alloc_ext_banks()
517 	return 0;  in ar5008_hw_rf_alloc_ext_banks()
538 	u32 ob5GHz = 0, db5GHz = 0;  in ar5008_hw_set_rf_regs()
539 	u32 ob2GHz = 0, db2GHz = 0;  in ar5008_hw_set_rf_regs()
540 	int regWrites = 0;  in ar5008_hw_set_rf_regs()
554 	for (i = 0; i < ah->iniBank6.ia_rows; i++)  in ar5008_hw_set_rf_regs()
563 						       ob2GHz, 3, 197, 0);  in ar5008_hw_set_rf_regs()
565 						       db2GHz, 3, 194, 0);  in ar5008_hw_set_rf_regs()
570 						       ob5GHz, 3, 203, 0);  in ar5008_hw_set_rf_regs()
572 						       db5GHz, 3, 200, 0);  in ar5008_hw_set_rf_regs()
608 	case 0x5:  in ar5008_hw_init_chain_masks()
612 	case 0x3:  in ar5008_hw_init_chain_masks()
614 			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);  in ar5008_hw_init_chain_masks()
615 			REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);  in ar5008_hw_init_chain_masks()
619 	case 0x1:  in ar5008_hw_init_chain_masks()
620 	case 0x2:  in ar5008_hw_init_chain_masks()
621 	case 0x7:  in ar5008_hw_init_chain_masks()
635 	if (tx_chainmask == 0x5) {  in ar5008_hw_init_chain_masks()
641 			  REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);  in ar5008_hw_init_chain_masks()
684 	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);  in ar5008_hw_override_ini()
701 	u32 enableDacFifo = 0;  in ar5008_hw_set_channel_regs()
725 	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);  in ar5008_hw_set_channel_regs()
735 	int i, regWrites = 0;  in ar5008_hw_process_ini()
750 	REG_WRITE(ah, AR_PHY(0), 0x00000007);  in ar5008_hw_process_ini()
762 	for (i = 0; i < ah->iniModes.ia_rows; i++) {  in ar5008_hw_process_ini()
763 		u32 reg = INI_RA(&ah->iniModes, i, 0);  in ar5008_hw_process_ini()
771 		if (reg >= 0x7800 && reg < 0x78a0  in ar5008_hw_process_ini()
791 		REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);  in ar5008_hw_process_ini()
797 	for (i = 0; i < ah->iniCommon.ia_rows; i++) {  in ar5008_hw_process_ini()
798 		u32 reg = INI_RA(&ah->iniCommon, i, 0);  in ar5008_hw_process_ini()
803 		if (reg >= 0x7800 && reg < 0x78a0  in ar5008_hw_process_ini()
832 	return 0;  in ar5008_hw_process_ini()
837 	u32 rfMode = 0;  in ar5008_hw_set_rfmode()
866 	u32 clockMhzScaled = 0x64000000;  in ar5008_hw_set_delta_slope()
909 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);  in ar5008_hw_rfbus_done()
916 	if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {  in ar5008_restore_chainmask()
927 	pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);  in ar9160_hw_compute_pll_control()
930 		pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);  in ar9160_hw_compute_pll_control()
932 		pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);  in ar9160_hw_compute_pll_control()
935 		pll |= SM(0x50, AR_RTC_9160_PLL_DIV);  in ar9160_hw_compute_pll_control()
937 		pll |= SM(0x58, AR_RTC_9160_PLL_DIV);  in ar9160_hw_compute_pll_control()
950 		pll |= SM(0x1, AR_RTC_PLL_CLKSEL);  in ar5008_hw_compute_pll_control()
952 		pll |= SM(0x2, AR_RTC_PLL_CLKSEL);  in ar5008_hw_compute_pll_control()
955 		pll |= SM(0xa, AR_RTC_PLL_DIV);  in ar5008_hw_compute_pll_control()
957 		pll |= SM(0xb, AR_RTC_PLL_DIV);  in ar5008_hw_compute_pll_control()
977 		 * on == 0 means ofdm weak signal detection is OFF  in ar5008_hw_ani_control_new()
978 		 * on == 0 means more noise imm  in ar5008_hw_ani_control_new()
980 		u32 on = param ? 1 : 0;  in ar5008_hw_ani_control_new()
1152 	nfarray[0] = sign_extend32(nf, 8);  in ar5008_hw_do_getnf()
1242 	u32 radar_0 = 0, radar_1;  in ar5008_hw_set_radar_params()
1289 #define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x))  in ar5008_hw_init_txpower_cck()
1290 	ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]);  in ar5008_hw_init_txpower_cck()
1303 	int i, idx = 0;  in ar5008_hw_init_txpower_ofdm()
1396 	return 0;  in ar5008_hw_attach_phy_ops()