Lines Matching full:u32
39 u32 cmd_id;
43 u32 header;
2107 u32 pdev_id;
2108 u32 start_freq;
2109 u32 end_freq;
2113 u32 numss_m1;
2114 u32 ru_bit_mask;
2115 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2119 u32 default_conc_scan_config_bits;
2120 u32 default_fw_config_bits;
2122 u32 he_cap_info;
2123 u32 mpdu_density;
2124 u32 max_bssid_rx_filters;
2125 u32 num_hw_modes;
2126 u32 num_phy;
2130 u32 hw_mode_id;
2131 u32 phy_id_map;
2132 u32 hw_mode_config_type;
2144 u32 phy_id;
2145 u32 eeprom_reg_domain;
2146 u32 eeprom_reg_domain_ext;
2147 u32 regcap1;
2148 u32 regcap2;
2149 u32 wireless_modes;
2150 u32 low_2ghz_chan;
2151 u32 high_2ghz_chan;
2152 u32 low_5ghz_chan;
2153 u32 high_5ghz_chan;
2159 u32 tlv_header;
2160 u32 req_id;
2161 u32 ptr;
2162 u32 size;
2168 u32 len;
2169 u32 req_id;
2173 u32 tlv_header;
2177 u32 hw_mode_id;
2178 u32 num_band_to_mac;
2183 u32 tlv_header;
2184 u32 pdev_id;
2185 u32 start_freq;
2186 u32 end_freq;
2190 u32 tlv_header;
2191 u32 pdev_id;
2192 u32 hw_mode_index;
2193 u32 num_band_to_mac;
2197 u32 numss_m1; /** NSS - 1*/
2199 u32 ru_count;
2200 u32 ru_mask;
2202 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2208 u32 abi_version_0;
2209 u32 abi_version_1;
2210 u32 abi_version_ns_0;
2211 u32 abi_version_ns_1;
2212 u32 abi_version_ns_2;
2213 u32 abi_version_ns_3;
2217 u32 tlv_header;
2219 u32 num_host_mem_chunks;
2223 u32 tlv_header;
2224 u32 num_vdevs;
2225 u32 num_peers;
2226 u32 num_offload_peers;
2227 u32 num_offload_reorder_buffs;
2228 u32 num_peer_keys;
2229 u32 num_tids;
2230 u32 ast_skid_limit;
2231 u32 tx_chain_mask;
2232 u32 rx_chain_mask;
2233 u32 rx_timeout_pri[4];
2234 u32 rx_decap_mode;
2235 u32 scan_max_pending_req;
2236 u32 bmiss_offload_max_vdev;
2237 u32 roam_offload_max_vdev;
2238 u32 roam_offload_max_ap_profiles;
2239 u32 num_mcast_groups;
2240 u32 num_mcast_table_elems;
2241 u32 mcast2ucast_mode;
2242 u32 tx_dbg_log_size;
2243 u32 num_wds_entries;
2244 u32 dma_burst_size;
2245 u32 mac_aggr_delim;
2246 u32 rx_skip_defrag_timeout_dup_detection_check;
2247 u32 vow_config;
2248 u32 gtk_offload_max_vdev;
2249 u32 num_msdu_desc;
2250 u32 max_frag_entries;
2251 u32 num_tdls_vdevs;
2252 u32 num_tdls_conn_table_entries;
2253 u32 beacon_tx_offload_max_vdev;
2254 u32 num_multicast_filter_entries;
2255 u32 num_wow_filters;
2256 u32 num_keep_alive_pattern;
2257 u32 keep_alive_pattern_size;
2258 u32 max_tdls_concurrent_sleep_sta;
2259 u32 max_tdls_concurrent_buffer_sta;
2260 u32 wmi_send_separate;
2261 u32 num_ocb_vdevs;
2262 u32 num_ocb_channels;
2263 u32 num_ocb_schedules;
2264 u32 flag1;
2265 u32 smart_ant_cap;
2266 u32 bk_minfree;
2267 u32 be_minfree;
2268 u32 vi_minfree;
2269 u32 vo_minfree;
2270 u32 alloc_frag_desc_for_data_pkt;
2271 u32 num_ns_ext_tuples_cfg;
2272 u32 bpf_instruction_size;
2273 u32 max_bssid_rx_filters;
2274 u32 use_pdev_id;
2275 u32 max_num_dbs_scan_duty_cycle;
2276 u32 max_num_group_keys;
2277 u32 peer_map_unmap_v2_support;
2278 u32 sched_params;
2279 u32 twt_ap_pdev_count;
2280 u32 twt_ap_sta_count;
2284 u32 fw_build_vers;
2286 u32 phy_capability;
2287 u32 max_frag_entry;
2288 u32 num_rf_chains;
2289 u32 ht_cap_info;
2290 u32 vht_cap_info;
2291 u32 vht_supp_mcs;
2292 u32 hw_min_tx_power;
2293 u32 hw_max_tx_power;
2294 u32 sys_cap_info;
2295 u32 min_pkt_size_enable;
2296 u32 max_bcn_ie_size;
2297 u32 num_mem_reqs;
2298 u32 max_num_scan_channels;
2299 u32 hw_bd_id;
2300 u32 hw_bd_info[HW_BD_INFO_SIZE];
2301 u32 max_supported_macs;
2302 u32 wmi_fw_sub_feat_caps;
2303 u32 num_dbs_hw_modes;
2310 u32 txrx_chainmask;
2311 u32 default_dbs_hw_mode_index;
2312 u32 num_msdu_desc;
2315 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2317 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2318 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2323 u32 default_conc_scan_config_bits;
2324 u32 default_fw_config_bits;
2326 u32 he_cap_info;
2327 u32 mpdu_density;
2328 u32 max_bssid_rx_filters;
2329 u32 fw_build_vers_ext;
2330 u32 max_nlo_ssids;
2331 u32 max_bssid_indicator;
2332 u32 he_cap_info_ext;
2336 u32 num_hw_modes;
2337 u32 num_chainmask_tables;
2341 u32 tlv_header;
2342 u32 hw_mode_id;
2343 u32 phy_id_map;
2344 u32 hw_mode_config_type;
2350 u32 hw_mode_id;
2351 u32 pdev_id;
2352 u32 phy_id;
2353 u32 supported_flags;
2354 u32 supported_bands;
2355 u32 ampdu_density;
2356 u32 max_bw_supported_2g;
2357 u32 ht_cap_info_2g;
2358 u32 vht_cap_info_2g;
2359 u32 vht_supp_mcs_2g;
2360 u32 he_cap_info_2g;
2361 u32 he_supp_mcs_2g;
2362 u32 tx_chain_mask_2g;
2363 u32 rx_chain_mask_2g;
2364 u32 max_bw_supported_5g;
2365 u32 ht_cap_info_5g;
2366 u32 vht_cap_info_5g;
2367 u32 vht_supp_mcs_5g;
2368 u32 he_cap_info_5g;
2369 u32 he_supp_mcs_5g;
2370 u32 tx_chain_mask_5g;
2371 u32 rx_chain_mask_5g;
2372 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2373 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2376 u32 chainmask_table_id;
2377 u32 lmac_id;
2378 u32 he_cap_info_2g_ext;
2379 u32 he_cap_info_5g_ext;
2380 u32 he_cap_info_internal;
2384 u32 tlv_header;
2385 u32 phy_id;
2386 u32 eeprom_reg_domain;
2387 u32 eeprom_reg_domain_ext;
2388 u32 regcap1;
2389 u32 regcap2;
2390 u32 wireless_modes;
2391 u32 low_2ghz_chan;
2392 u32 high_2ghz_chan;
2393 u32 low_5ghz_chan;
2394 u32 high_5ghz_chan;
2398 u32 num_phy;
2406 u32 word0;
2407 u32 word1;
2413 u32 tlv_header;
2414 u32 pdev_id;
2415 u32 module_id;
2416 u32 min_elem;
2417 u32 min_buf_sz;
2418 u32 min_buf_align;
2424 u32 status;
2425 u32 num_dscp_table;
2426 u32 num_extra_mac_addr;
2427 u32 num_total_peers;
2428 u32 num_extra_peers;
2433 u32 max_ast_index;
2434 u32 pktlog_defs_checksum;
2438 u32 wmi_service_segment_offset;
2439 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2446 u32 rx_decap_mode;
2451 u32 type;
2452 u32 subtype;
2457 u32 pdev_id;
2461 u32 tlv_header;
2462 u32 vdev_id;
2463 u32 vdev_type;
2464 u32 vdev_subtype;
2466 u32 num_cfg_txrx_streams;
2467 u32 pdev_id;
2471 u32 tlv_header;
2472 u32 band;
2473 u32 supported_tx_streams;
2474 u32 supported_rx_streams;
2478 u32 tlv_header;
2479 u32 vdev_id;
2483 u32 tlv_header;
2484 u32 vdev_id;
2485 u32 vdev_assoc_id;
2488 u32 profile_idx;
2489 u32 profile_num;
2493 u32 tlv_header;
2494 u32 vdev_id;
2498 u32 tlv_header;
2499 u32 vdev_id;
2507 u32 ssid_len;
2508 u32 ssid[8];
2514 u32 tlv_header;
2515 u32 vdev_id;
2516 u32 requestor_id;
2517 u32 beacon_interval;
2518 u32 dtim_period;
2519 u32 flags;
2521 u32 bcn_tx_rate;
2522 u32 bcn_txpower;
2523 u32 num_noa_descriptors;
2524 u32 disable_hw_ack;
2525 u32 preferred_tx_streams;
2526 u32 preferred_rx_streams;
2527 u32 he_ops;
2528 u32 cac_duration_ms;
2529 u32 regdomain;
2540 u32 type_count;
2541 u32 duration;
2542 u32 interval;
2543 u32 start_time;
2549 u32 mhz;
2550 u32 half_rate:1,
2560 u32 phy_mode;
2561 u32 cfreq1;
2562 u32 cfreq2;
2663 u32 freq;
2664 u32 band_center_freq1;
2665 u32 band_center_freq2;
2674 u32 min_power;
2675 u32 max_power;
2676 u32 max_reg_power;
2677 u32 max_antenna_gain;
2682 u32 vdev_id;
2684 u32 bcn_intval;
2685 u32 dtim_period;
2687 u32 ssid_len;
2688 u32 bcn_tx_rate;
2689 u32 bcn_tx_power;
2693 u32 he_ops;
2694 u32 cac_duration_ms;
2695 u32 regdomain;
2696 u32 pref_rx_streams;
2697 u32 pref_tx_streams;
2698 u32 num_noa_descriptors;
2703 u32 peer_type;
2704 u32 vdev_id;
2712 u32 peer_tid_bitmap;
2720 u32 ctl_2g;
2721 u32 ctl_5g;
2723 u32 pdev_id;
2729 u32 peer_tid_bitmap;
2811 u32 param_id;
2812 u32 param_value;
2822 u32 tlv_header;
2823 u32 vdev_id;
2825 u32 peer_type;
2829 u32 tlv_header;
2830 u32 vdev_id;
2835 u32 tlv_header;
2836 u32 vdev_id;
2838 u32 tid;
2839 u32 queue_ptr_lo;
2840 u32 queue_ptr_hi;
2841 u32 queue_no;
2842 u32 ba_window_size_valid;
2843 u32 ba_window_size;
2847 u32 tlv_header;
2848 u32 vdev_id;
2850 u32 tid_mask;
2854 u32 gpio_num;
2855 u32 input;
2856 u32 pull_type;
2857 u32 intr_mode;
2881 u32 tlv_header;
2882 u32 gpio_num;
2883 u32 input;
2884 u32 pull_type;
2885 u32 intr_mode;
2889 u32 gpio_num;
2890 u32 set;
2894 u32 tlv_header;
2895 u32 gpio_num;
2896 u32 set;
2900 u32 arg;
2901 u32 value;
2905 u32 tlv_header;
2906 u32 param_id;
2907 u32 param_value;
2911 u32 tlv_header;
2912 u32 pdev_id;
2913 u32 param_id;
2914 u32 param_value;
2918 u32 tlv_header;
2919 u32 vdev_id;
2920 u32 sta_ps_mode;
2924 u32 tlv_header;
2925 u32 pdev_id;
2926 u32 suspend_opt;
2930 u32 tlv_header;
2931 u32 pdev_id;
2935 u32 tlv_header;
2937 u32 req_type;
2941 u32 tlv_header;
2942 u32 vdev_id;
2944 u32 param;
2945 u32 value;
2949 u32 tlv_header;
2950 u32 vdev_id;
2951 u32 param;
2952 u32 value;
2956 u32 tlv_header;
2957 u32 pdev_id;
2958 u32 reg_domain;
2959 u32 reg_domain_2g;
2960 u32 reg_domain_5g;
2961 u32 conformance_test_limit_2g;
2962 u32 conformance_test_limit_5g;
2963 u32 dfs_domain;
2967 u32 tlv_header;
2968 u32 vdev_id;
2970 u32 param_id;
2971 u32 param_value;
2975 u32 tlv_header;
2976 u32 vdev_id;
2978 u32 peer_tid_bitmap;
2982 u32 tlv_header;
2983 u32 pdev_id;
2987 u32 tlv_header;
2988 u32 vdev_id;
2989 u32 bcn_ctrl_op;
3007 u32 len;
3071 u32 tlv_header;
3072 u32 scan_id;
3073 u32 scan_req_id;
3074 u32 vdev_id;
3075 u32 scan_priority;
3076 u32 notify_scan_events;
3077 u32 dwell_time_active;
3078 u32 dwell_time_passive;
3079 u32 min_rest_time;
3080 u32 max_rest_time;
3081 u32 repeat_probe_time;
3082 u32 probe_spacing_time;
3083 u32 idle_time;
3084 u32 max_scan_time;
3085 u32 probe_delay;
3086 u32 scan_ctrl_flags;
3087 u32 burst_duration;
3088 u32 num_chan;
3089 u32 num_bssid;
3090 u32 num_ssids;
3091 u32 ie_len;
3092 u32 n_probes;
3095 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3096 u32 num_vendor_oui;
3097 u32 scan_ctrl_flags_ext;
3098 u32 dwell_time_active_2g;
3099 u32 dwell_time_active_6g;
3100 u32 dwell_time_passive_6g;
3101 u32 scan_start_offset;
3142 u32 freq_flags;
3143 u32 short_ssid;
3147 u32 freq_flags;
3152 u32 scan_id;
3153 u32 scan_req_id;
3154 u32 vdev_id;
3155 u32 pdev_id;
3159 u32 scan_ev_started:1,
3173 u32 scan_events;
3175 u32 dwell_time_active;
3176 u32 dwell_time_active_2g;
3177 u32 dwell_time_passive;
3178 u32 dwell_time_active_6g;
3179 u32 dwell_time_passive_6g;
3180 u32 min_rest_time;
3181 u32 max_rest_time;
3182 u32 repeat_probe_time;
3183 u32 probe_spacing_time;
3184 u32 idle_time;
3185 u32 max_scan_time;
3186 u32 probe_delay;
3189 u32 scan_f_passive:1,
3215 u32 scan_flags;
3218 u32 burst_duration;
3219 u32 num_chan;
3220 u32 num_bssid;
3221 u32 num_ssids;
3222 u32 n_probes;
3223 u32 chan_list[WLAN_SCAN_MAX_NUM_CHANNELS];
3224 u32 notify_scan_events;
3230 u32 num_hint_s_ssid;
3231 u32 num_hint_bssid;
3246 u32 scan_id;
3247 u32 scan_req_id;
3248 u32 vdev_id;
3249 u32 scan_priority;
3250 u32 notify_scan_events;
3251 u32 dwell_time_active;
3252 u32 dwell_time_passive;
3253 u32 min_rest_time;
3254 u32 max_rest_time;
3255 u32 repeat_probe_time;
3256 u32 probe_spacing_time;
3257 u32 idle_time;
3258 u32 max_scan_time;
3259 u32 probe_delay;
3260 u32 scan_ctrl_flags;
3262 u32 ie_len;
3263 u32 n_channels;
3264 u32 n_ssids;
3265 u32 n_bssids;
3268 u32 channels[64];
3289 u32 requester;
3290 u32 scan_id;
3292 u32 vdev_id;
3293 u32 pdev_id;
3297 u32 tlv_header;
3298 u32 vdev_id;
3299 u32 data_len;
3301 u32 frag_ptr;
3302 u32 frag_ptr_lo;
3304 u32 frame_ctrl;
3305 u32 dtim_flag;
3306 u32 bcn_antenna;
3307 u32 frag_ptr_hi;
3334 u32 tlv_header;
3335 u32 mhz;
3336 u32 band_center_freq1;
3337 u32 band_center_freq2;
3338 u32 info;
3339 u32 reg_info_1;
3340 u32 reg_info_2;
3371 u32 tlv_header;
3372 u32 type;
3373 u32 delay_time_ms;
3377 u32 tlv_header;
3378 u32 vdev_id;
3379 u32 param_id;
3380 u32 param_value;
3401 u32 tlv_header;
3403 u32 vdev_id;
3405 u32 pdev_id;
3409 u32 tlv_header;
3410 u32 param;
3411 u32 pdev_id;
3417 u32 tlv_header;
3418 u32 vdev_id;
3419 u32 tim_ie_offset;
3420 u32 buf_len;
3421 u32 csa_switch_count_offset;
3422 u32 ext_csa_switch_count_offset;
3423 u32 csa_event_bitmap;
3424 u32 mbssid_ie_offset;
3425 u32 esp_ie_offset;
3429 u32 key_seq_counter_l;
3430 u32 key_seq_counter_h;
3434 u32 tlv_header;
3435 u32 vdev_id;
3437 u32 key_idx;
3438 u32 key_flags;
3439 u32 key_cipher;
3445 u32 key_len;
3446 u32 key_txmic_len;
3447 u32 key_rxmic_len;
3448 u32 is_group_key_id_valid;
3449 u32 group_key_id;
3457 u32 vdev_id;
3459 u32 key_idx;
3460 u32 key_flags;
3461 u32 key_cipher;
3462 u32 key_len;
3463 u32 key_txmic_len;
3464 u32 key_rxmic_len;
3477 u32 num_rates;
3483 u32 vdev_id;
3484 u32 peer_new_assoc;
3485 u32 peer_associd;
3486 u32 peer_flags;
3487 u32 peer_caps;
3488 u32 peer_listen_intval;
3489 u32 peer_ht_caps;
3490 u32 peer_max_mpdu;
3491 u32 peer_mpdu_density;
3492 u32 peer_rate_caps;
3493 u32 peer_nss;
3494 u32 peer_vht_caps;
3495 u32 peer_phymode;
3496 u32 peer_ht_info[2];
3499 u32 rx_max_rate;
3500 u32 rx_mcs_set;
3501 u32 tx_max_rate;
3502 u32 tx_mcs_set;
3505 u32 tx_max_mcs_nss;
3506 u32 peer_bw_rxnss_override;
3531 u32 peer_he_cap_macinfo[2];
3532 u32 peer_he_cap_macinfo_internal;
3533 u32 peer_he_caps_6ghz;
3534 u32 peer_he_ops;
3535 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3536 u32 peer_he_mcs_count;
3537 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3538 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3545 u32 tlv_header;
3547 u32 vdev_id;
3548 u32 peer_new_assoc;
3549 u32 peer_associd;
3550 u32 peer_flags;
3551 u32 peer_caps;
3552 u32 peer_listen_intval;
3553 u32 peer_ht_caps;
3554 u32 peer_max_mpdu;
3555 u32 peer_mpdu_density;
3556 u32 peer_rate_caps;
3557 u32 peer_nss;
3558 u32 peer_vht_caps;
3559 u32 peer_phymode;
3560 u32 peer_ht_info[2];
3561 u32 num_peer_legacy_rates;
3562 u32 num_peer_ht_rates;
3563 u32 peer_bw_rxnss_override;
3565 u32 peer_he_cap_info;
3566 u32 peer_he_ops;
3567 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3568 u32 peer_he_mcs;
3569 u32 peer_he_cap_info_ext;
3570 u32 peer_he_cap_info_internal;
3571 u32 min_data_rate;
3572 u32 peer_he_caps_6ghz;
3576 u32 tlv_header;
3577 u32 requestor;
3578 u32 scan_id;
3579 u32 req_type;
3580 u32 vdev_id;
3581 u32 pdev_id;
3585 u32 pdev_id;
3591 u32 tlv_header;
3592 u32 num_scan_chans;
3593 u32 flags;
3594 u32 pdev_id;
3611 u32 tlv_header;
3612 u32 tx_params_dword0;
3613 u32 tx_params_dword1;
3617 u32 tlv_header;
3618 u32 vdev_id;
3619 u32 desc_id;
3620 u32 chanfreq;
3621 u32 paddr_lo;
3622 u32 paddr_hi;
3623 u32 frame_len;
3624 u32 buf_len;
3625 u32 tx_params_valid;
3633 u32 tlv_header;
3634 u32 vdev_id;
3635 u32 sta_ps_mode;
3639 u32 tlv_header;
3640 u32 vdev_id;
3641 u32 forced_mode;
3645 u32 tlv_header;
3646 u32 vdev_id;
3647 u32 param;
3648 u32 value;
3652 u32 tlv_header;
3653 u32 caps;
3654 u32 erp;
3663 u32 value;
3667 u32 tlv_header;
3668 u32 pdev_id;
3669 u32 enable;
3673 u32 vdev_id;
3674 u32 param;
3675 u32 value;
3679 u32 if_id;
3680 u32 param_id;
3681 u32 param_value;
3685 u32 stats_id;
3686 u32 vdev_id;
3687 u32 pdev_id;
3713 u32 tlv_header;
3714 u32 pdev_id;
3715 u32 init_cc_type;
3717 u32 country_code;
3718 u32 regdom_id;
3719 u32 alpha2;
3725 u32 tmplwm;
3726 u32 tmphwm;
3727 u32 dcoffpercent;
3728 u32 priority;
3732 u32 pdev_id;
3733 u32 enable;
3734 u32 dc;
3735 u32 dc_per_event;
3740 u32 tlv_header;
3741 u32 pdev_id;
3742 u32 enable;
3743 u32 dc;
3744 u32 dc_per_event;
3745 u32 therm_throt_levels;
3749 u32 tlv_header;
3750 u32 temp_lwm;
3751 u32 temp_hwm;
3752 u32 dc_off_percent;
3753 u32 prio;
3757 u32 tlv_header;
3758 u32 vdev_id;
3760 u32 tid;
3761 u32 initiator;
3762 u32 reasoncode;
3766 u32 tlv_header;
3767 u32 vdev_id;
3769 u32 tid;
3770 u32 statuscode;
3774 u32 tlv_header;
3775 u32 vdev_id;
3777 u32 tid;
3778 u32 buffersize;
3782 u32 tlv_header;
3783 u32 vdev_id;
3788 u32 tlv_header;
3793 u32 tlv_header;
3794 u32 pdev_id;
3795 u32 enable;
3796 u32 filter_type;
3797 u32 num_mac;
3806 u32 tlv_header;
3807 u32 pdev_id;
3808 u32 evlist; /* WMI_PKTLOG_EVENT */
3809 u32 enable;
3813 u32 tlv_header;
3814 u32 pdev_id;
3829 u32 cmd_id;
3830 u32 pdev_id;
3831 u32 radar_param;
3835 u32 tlv_header;
3836 u32 vdev_id;
3837 u32 module_id;
3838 u32 num_args;
3839 u32 diag_token;
3872 u32 tim_ie_offset;
3873 u32 tmpl_len;
3874 u32 tmpl_len_aligned;
3875 u32 csa_switch_count_offset;
3876 u32 ext_csa_switch_count_offset;
3881 u32 num_rates;
3882 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
3886 u32 tlv_header;
3887 u32 rx_max_rate;
3888 u32 rx_mcs_set;
3889 u32 tx_max_rate;
3890 u32 tx_mcs_set;
3891 u32 tx_max_mcs_nss;
3895 u32 tlv_header;
3896 u32 rx_mcs_set;
3897 u32 tx_mcs_set;
3909 u32 vdev_id;
3910 u32 requestor_id;
3912 u32 status;
3913 u32 chain_mask;
3914 u32 smps_mode;
3916 u32 mac_id;
3917 u32 pdev_id;
3919 u32 cfgd_tx_streams;
3920 u32 cfgd_rx_streams;
3980 u32 dfs_region;
3981 u32 phybitmap;
3982 u32 min_bw_2g;
3983 u32 max_bw_2g;
3984 u32 min_bw_5g;
3985 u32 max_bw_5g;
3986 u32 num_2g_reg_rules;
3987 u32 num_5g_reg_rules;
3993 u32 status_code;
3994 u32 phy_id;
3995 u32 alpha2;
3996 u32 num_phy;
3997 u32 country_id;
3998 u32 domain_code;
3999 u32 dfs_region;
4000 u32 phybitmap;
4001 u32 min_bw_2g;
4002 u32 max_bw_2g;
4003 u32 min_bw_5g;
4004 u32 max_bw_5g;
4005 u32 num_2g_reg_rules;
4006 u32 num_5g_reg_rules;
4010 u32 tlv_header;
4011 u32 freq_info;
4012 u32 bw_pwr_info;
4013 u32 flag_info;
4017 u32 vdev_id;
4022 u32 vdev_id;
4023 u32 tx_status;
4027 u32 vdev_id;
4031 u32 pdev_id;
4032 u32 freq; /* Units in MHz */
4033 u32 noise_floor; /* units are dBm */
4035 u32 rx_clear_count_low;
4036 u32 rx_clear_count_high;
4038 u32 cycle_count_low;
4039 u32 cycle_count_high;
4041 u32 tx_cycle_count_low;
4042 u32 tx_cycle_count_high;
4044 u32 rx_cycle_count_low;
4045 u32 rx_cycle_count_high;
4047 u32 rx_bss_cycle_count_low;
4048 u32 rx_bss_cycle_count_high;
4054 u32 vdev_id;
4056 u32 key_idx;
4057 u32 key_flags;
4058 u32 status;
4062 u32 vdev_id;
4064 u32 key_idx;
4065 u32 key_flags;
4066 u32 status;
4070 u32 vdev_id;
4075 u32 vdev_id;
4084 u32 tx_frame_count; /* Cycles spent transmitting frames */
4085 u32 rx_frame_count; /* Cycles spent receiving frames */
4086 u32 rx_clear_count; /* Total channel busy time, evidently */
4087 u32 cycle_count; /* Total on-channel time */
4088 u32 phy_err_count;
4089 u32 chan_tx_pwr;
4093 u32 ack_rx_bad;
4094 u32 rts_bad;
4095 u32 rts_good;
4096 u32 fcs_bad;
4097 u32 no_beacons;
4098 u32 mib_int_count;
4139 u32 tx_ko;
4142 u32 data_rc;
4145 u32 self_triggers;
4148 u32 sw_retry_failure;
4151 u32 illgl_rate_phy_err;
4154 u32 pdev_cont_xretry;
4157 u32 pdev_tx_timeout;
4160 u32 pdev_resets;
4163 u32 stateless_tid_alloc_failure;
4166 u32 phy_underrun;
4169 u32 txop_ovf;
4217 u32 vdev_id;
4218 u32 beacon_snr;
4219 u32 data_snr;
4220 u32 num_tx_frames[WLAN_MAX_AC];
4221 u32 num_rx_frames;
4222 u32 num_tx_frames_retries[WLAN_MAX_AC];
4223 u32 num_tx_frames_failures[WLAN_MAX_AC];
4224 u32 num_rts_fail;
4225 u32 num_rts_success;
4226 u32 num_rx_err;
4227 u32 num_rx_discard;
4228 u32 num_tx_not_acked;
4229 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4230 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4234 u32 vdev_id;
4235 u32 tx_bcn_succ_cnt;
4236 u32 tx_bcn_outage_cnt;
4240 u32 stats_id;
4241 u32 num_pdev_stats;
4242 u32 num_vdev_stats;
4243 u32 num_peer_stats;
4244 u32 num_bcnflt_stats;
4245 u32 num_chan_stats;
4246 u32 num_mib_stats;
4247 u32 pdev_id;
4248 u32 num_bcn_stats;
4249 u32 num_peer_extd_stats;
4250 u32 num_peer_extd2_stats;
4254 u32 pdev_id;
4255 u32 ctl_failsafe_status;
4259 u32 pdev_id;
4260 u32 current_switch_count;
4261 u32 num_vdevs;
4265 u32 pdev_id;
4266 u32 detection_mode;
4267 u32 chan_freq;
4268 u32 chan_width;
4269 u32 detector_id;
4270 u32 segment_id;
4271 u32 timestamp;
4272 u32 is_chirp;
4280 u32 pdev_id;
4292 u32 chan_freq;
4293 u32 channel;
4294 u32 snr;
4296 u32 rate;
4298 u32 buf_len;
4300 u32 flags;
4302 u32 tsf_delta;
4309 u32 channel;
4310 u32 snr;
4311 u32 rate;
4312 u32 phy_mode;
4313 u32 buf_len;
4314 u32 status;
4315 u32 rssi_ctl[ATH_MAX_ANTENNA];
4316 u32 flags;
4318 u32 tsf_delta;
4319 u32 rx_tsf_l32;
4320 u32 rx_tsf_u32;
4321 u32 pdev_id;
4322 u32 chan_freq;
4328 u32 tlv_header;
4329 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4333 u32 desc_id;
4334 u32 status;
4335 u32 pdev_id;
4339 u32 event_type; /* %WMI_SCAN_EVENT_ */
4340 u32 reason; /* %WMI_SCAN_REASON_ */
4341 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4342 u32 scan_req_id;
4343 u32 scan_id;
4344 u32 vdev_id;
4350 u32 tsf_timestamp;
4373 u32 vdev_id;
4374 u32 reason;
4375 u32 rssi;
4382 u32 err_code;
4383 u32 freq;
4384 u32 cmd_flags;
4385 u32 noise_floor;
4386 u32 rx_clear_count;
4387 u32 cycle_count;
4388 u32 chan_tx_pwr_range;
4389 u32 chan_tx_pwr_tp;
4390 u32 rx_frame_count;
4391 u32 my_bss_rx_cycle_count;
4392 u32 rx_11b_mode_data_duration;
4393 u32 tx_frame_cnt;
4394 u32 mac_clk_mhz;
4395 u32 vdev_id;
4399 u32 phy_capability;
4400 u32 max_frag_entry;
4401 u32 num_rf_chains;
4402 u32 ht_cap_info;
4403 u32 vht_cap_info;
4404 u32 vht_supp_mcs;
4405 u32 hw_min_tx_power;
4406 u32 hw_max_tx_power;
4407 u32 sys_cap_info;
4408 u32 min_pkt_size_enable;
4409 u32 max_bcn_ie_size;
4410 u32 max_num_scan_channels;
4411 u32 max_supported_macs;
4412 u32 wmi_fw_sub_feat_caps;
4413 u32 txrx_chainmask;
4414 u32 default_dbs_hw_mode_index;
4415 u32 num_msdu_desc;
4464 u32 wmm_ac;
4465 u32 user_priority;
4466 u32 service_interval;
4467 u32 suspend_interval;
4468 u32 delay_interval;
4472 u32 vdev_id;
4474 u32 num_ac;
4478 u32 wmm_ac;
4479 u32 user_priority;
4480 u32 service_interval;
4481 u32 suspend_interval;
4482 u32 delay_interval;
4646 u32 eeprom_rd;
4647 u32 eeprom_rd_ext;
4648 u32 regcap1;
4649 u32 regcap2;
4650 u32 wireless_modes;
4651 u32 low_2ghz_chan;
4652 u32 high_2ghz_chan;
4653 u32 low_5ghz_chan;
4654 u32 high_5ghz_chan;
4660 u32 len;
4661 u32 req_id;
4681 u32 tlv_header;
4682 u32 cwmin;
4683 u32 cwmax;
4684 u32 aifs;
4685 u32 txoplimit;
4686 u32 acm;
4687 u32 no_ack;
4700 u32 tlv_header;
4701 u32 vdev_id;
4703 u32 wmm_param_type;
4730 u32 tlv_header;
4731 u32 pdev_id;
4732 u32 sta_cong_timer_ms;
4733 u32 mbss_support;
4734 u32 default_slot_size;
4735 u32 congestion_thresh_setup;
4736 u32 congestion_thresh_teardown;
4737 u32 congestion_thresh_critical;
4738 u32 interference_thresh_teardown;
4739 u32 interference_thresh_setup;
4740 u32 min_no_sta_setup;
4741 u32 min_no_sta_teardown;
4742 u32 no_of_bcast_mcast_slots;
4743 u32 min_no_twt_slots;
4744 u32 max_no_sta_twt;
4745 u32 mode_check_interval;
4746 u32 add_sta_slot_interval;
4747 u32 remove_sta_slot_interval;
4751 u32 tlv_header;
4752 u32 pdev_id;
4756 u32 tlv_header;
4757 u32 pdev_id;
4758 u32 enable;
4761 u32 vdev_id;
4772 u32 tlv_header;
4773 u32 vdev_id;
4774 u32 flags;
4775 u32 evt_type;
4776 u32 current_bss_color;
4777 u32 detection_period_ms;
4778 u32 scan_period_ms;
4779 u32 free_slot_expiry_time_ms;
4783 u32 tlv_header;
4784 u32 vdev_id;
4785 u32 enable;
4792 u32 tlv_header;
4793 u32 lro_enable;
4794 u32 res;
4795 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
4796 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
4797 u32 pdev_id;
4820 u32 vdev_id;
4821 u32 scan_count;
4822 u32 scan_period;
4823 u32 scan_priority;
4824 u32 scan_fft_size;
4825 u32 scan_gc_ena;
4826 u32 scan_restart_ena;
4827 u32 scan_noise_floor_ref;
4828 u32 scan_init_delay;
4829 u32 scan_nb_tone_thr;
4830 u32 scan_str_bin_thr;
4831 u32 scan_wb_rpt_mode;
4832 u32 scan_rssi_rpt_mode;
4833 u32 scan_rssi_thr;
4834 u32 scan_pwr_format;
4835 u32 scan_rpt_mode;
4836 u32 scan_bin_scale;
4837 u32 scan_dbm_adj;
4838 u32 scan_chn_mask;
4842 u32 tlv_header;
4852 u32 tlv_header;
4853 u32 vdev_id;
4854 u32 trigger_cmd;
4855 u32 enable_cmd;
4859 u32 tlv_header;
4860 u32 pdev_id;
4861 u32 module_id; /* see enum wmi_direct_buffer_module */
4862 u32 base_paddr_lo;
4863 u32 base_paddr_hi;
4864 u32 head_idx_paddr_lo;
4865 u32 head_idx_paddr_hi;
4866 u32 tail_idx_paddr_lo;
4867 u32 tail_idx_paddr_hi;
4868 u32 num_elems; /* Number of elems in the ring */
4869 u32 buf_size; /* size of allocated buffer in bytes */
4872 u32 num_resp_per_event;
4877 u32 event_timeout_ms;
4881 u32 pdev_id;
4882 u32 module_id;
4883 u32 num_buf_release_entry;
4884 u32 num_meta_data_entry;
4888 u32 tlv_header;
4889 u32 paddr_lo;
4894 u32 paddr_hi;
4903 u32 tlv_header;
4905 u32 reset_delay;
4906 u32 freq1;
4907 u32 freq2;
4908 u32 ch_width;
4912 u32 num_vdevs;
4913 u32 num_peers;
4914 u32 num_active_peers;
4915 u32 num_offload_peers;
4916 u32 num_offload_reorder_buffs;
4917 u32 num_peer_keys;
4918 u32 num_tids;
4919 u32 ast_skid_limit;
4920 u32 tx_chain_mask;
4921 u32 rx_chain_mask;
4922 u32 rx_timeout_pri[4];
4923 u32 rx_decap_mode;
4924 u32 scan_max_pending_req;
4925 u32 bmiss_offload_max_vdev;
4926 u32 roam_offload_max_vdev;
4927 u32 roam_offload_max_ap_profiles;
4928 u32 num_mcast_groups;
4929 u32 num_mcast_table_elems;
4930 u32 mcast2ucast_mode;
4931 u32 tx_dbg_log_size;
4932 u32 num_wds_entries;
4933 u32 dma_burst_size;
4934 u32 mac_aggr_delim;
4935 u32 rx_skip_defrag_timeout_dup_detection_check;
4936 u32 vow_config;
4937 u32 gtk_offload_max_vdev;
4938 u32 num_msdu_desc;
4939 u32 max_frag_entries;
4940 u32 max_peer_ext_stats;
4941 u32 smart_ant_cap;
4942 u32 bk_minfree;
4943 u32 be_minfree;
4944 u32 vi_minfree;
4945 u32 vo_minfree;
4946 u32 rx_batchmode;
4947 u32 tt_support;
4948 u32 atf_config;
4949 u32 iphdr_pad_config;
4950 u32 qwrap_config:16,
4952 u32 num_tdls_vdevs;
4953 u32 num_tdls_conn_table_entries;
4954 u32 beacon_tx_offload_max_vdev;
4955 u32 num_multicast_filter_entries;
4956 u32 num_wow_filters;
4957 u32 num_keep_alive_pattern;
4958 u32 keep_alive_pattern_size;
4959 u32 max_tdls_concurrent_sleep_sta;
4960 u32 max_tdls_concurrent_buffer_sta;
4961 u32 wmi_send_separate;
4962 u32 num_ocb_vdevs;
4963 u32 num_ocb_channels;
4964 u32 num_ocb_schedules;
4965 u32 num_ns_ext_tuples_cfg;
4966 u32 bpf_instruction_size;
4967 u32 max_bssid_rx_filters;
4968 u32 use_pdev_id;
4969 u32 peer_map_unmap_v2_support;
4970 u32 sched_params;
4971 u32 twt_ap_pdev_count;
4972 u32 twt_ap_sta_count;
4986 u32 max_msg_len[MAX_RADIOS];
4993 u32 num_mem_chunks;
4994 u32 rx_decap_mode;
5004 u32 cmd_id);
5005 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
5006 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
5008 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
5012 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
5018 u32 vdev_id, u32 param_id, u32 param_val);
5019 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
5020 u32 param_value, u8 pdev_id);
5021 int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id, u32 enable);
5035 u32 ba_window_size);
5038 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
5039 u32 param_id, u32 param_value);
5041 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
5042 u32 param, u32 param_value);
5043 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
5052 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
5054 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
5055 u32 pdev_id);
5056 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
5075 u32 pdev_id);
5076 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
5077 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5078 u32 tid, u32 buf_size);
5079 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5080 u32 tid, u32 status);
5081 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5082 u32 tid, u32 initiator, u32 reason);
5084 u32 vdev_id, u32 bcn_ctrl_op);
5091 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
5105 struct ath11k_fw_stats *fw_stats, u32 stats_id,
5108 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id);
5109 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
5110 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
5112 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
5113 u8 bss_color, u32 period,
5115 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
5120 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
5121 u32 trigger, u32 enable);