18 	case 0:  in ath11k_hw_ipq8074_mac_from_pdev_id()
19 		return 0;  in ath11k_hw_ipq8074_mac_from_pdev_id()
47 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;  in ath11k_init_wmi_config_qca6390()
56 	config->num_mcast_groups = 0;  in ath11k_init_wmi_config_qca6390()
57 	config->num_mcast_table_elems = 0;  in ath11k_init_wmi_config_qca6390()
58 	config->mcast2ucast_mode = 0;  in ath11k_init_wmi_config_qca6390()
60 	config->num_wds_entries = 0;  in ath11k_init_wmi_config_qca6390()
61 	config->dma_burst_size = 0;  in ath11k_init_wmi_config_qca6390()
62 	config->rx_skip_defrag_timeout_dup_detection_check = 0;  in ath11k_init_wmi_config_qca6390()
65 	config->num_msdu_desc = 0x400;  in ath11k_init_wmi_config_qca6390()
69 	config->peer_map_unmap_v2_support = 0;  in ath11k_init_wmi_config_qca6390()
71 	config->max_frag_entries = 0xa;  in ath11k_init_wmi_config_qca6390()
72 	config->num_tdls_vdevs = 0x1;  in ath11k_init_wmi_config_qca6390()
74 	config->beacon_tx_offload_max_vdev = 0x2;  in ath11k_init_wmi_config_qca6390()
75 	config->num_multicast_filter_entries = 0x20;  in ath11k_init_wmi_config_qca6390()
76 	config->num_wow_filters = 0x16;  in ath11k_init_wmi_config_qca6390()
77 	config->num_keep_alive_pattern = 0;  in ath11k_init_wmi_config_qca6390()
102 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;  in ath11k_init_wmi_config_ipq8074()
143 	return 0;  in ath11k_hw_mac_id_to_srng_id_ipq8074()
149 	return 0;  in ath11k_hw_mac_id_to_pdev_id_qca6390()
179 #define ATH11K_TX_RING_MASK_0 0x1
180 #define ATH11K_TX_RING_MASK_1 0x2
181 #define ATH11K_TX_RING_MASK_2 0x4
183 #define ATH11K_RX_RING_MASK_0 0x1
184 #define ATH11K_RX_RING_MASK_1 0x2
185 #define ATH11K_RX_RING_MASK_2 0x4
186 #define ATH11K_RX_RING_MASK_3 0x8
188 #define ATH11K_RX_ERR_RING_MASK_0 0x1
190 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
192 #define ATH11K_REO_STATUS_RING_MASK_0 0x1
194 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
195 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
196 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
198 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
199 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
200 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
202 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
203 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
204 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
213 		0, 0, 0, 0,
219 		0, 0, 0, 0, 0, 0, 0,
253 		0, 0, 0, 0,
259 		0, 0, 0, 0, 0, 0, 0,
287 		.pipenum = __cpu_to_le32(0),
292 		.reserved = __cpu_to_le32(0),
302 		.reserved = __cpu_to_le32(0),
312 		.reserved = __cpu_to_le32(0),
322 		.reserved = __cpu_to_le32(0),
332 		.reserved = __cpu_to_le32(0),
341 		.flags = __cpu_to_le32(0),
342 		.reserved = __cpu_to_le32(0),
352 		.reserved = __cpu_to_le32(0),
362 		.reserved = __cpu_to_le32(0),
372 		.reserved = __cpu_to_le32(0),
382 		.reserved = __cpu_to_le32(0),
389 		.nentries = __cpu_to_le32(0),
390 		.nbytes_max = __cpu_to_le32(0),
392 		.reserved = __cpu_to_le32(0),
476 		.pipenum = __cpu_to_le32(0),
486 		.pipenum = __cpu_to_le32(0),
578 		.pipenum = __cpu_to_le32(0),
588 		.pipenum = __cpu_to_le32(0),
620 		.pipenum = __cpu_to_le32(0),
625 		.reserved = __cpu_to_le32(0),
635 		.reserved = __cpu_to_le32(0),
645 		.reserved = __cpu_to_le32(0),
655 		.reserved = __cpu_to_le32(0),
665 		.reserved = __cpu_to_le32(0),
675 		.reserved = __cpu_to_le32(0),
685 		.reserved = __cpu_to_le32(0),
692 		.nentries = __cpu_to_le32(0),
693 		.nbytes_max = __cpu_to_le32(0),
695 		.reserved = __cpu_to_le32(0),
705 		.reserved = __cpu_to_le32(0),
768 		__cpu_to_le32(0),
789 		__cpu_to_le32(0),
790 		__cpu_to_le32(0),
791 		__cpu_to_le32(0),
797 	.hal_tcl1_ring_base_lsb = 0x00000510,
798 	.hal_tcl1_ring_base_msb = 0x00000514,
799 	.hal_tcl1_ring_id = 0x00000518,
800 	.hal_tcl1_ring_misc = 0x00000520,
801 	.hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
802 	.hal_tcl1_ring_tp_addr_msb = 0x00000530,
803 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
804 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
805 	.hal_tcl1_ring_msi1_base_lsb = 0x00000558,
806 	.hal_tcl1_ring_msi1_base_msb = 0x0000055c,
807 	.hal_tcl1_ring_msi1_data = 0x00000560,
808 	.hal_tcl2_ring_base_lsb = 0x00000568,
809 	.hal_tcl_ring_base_lsb = 0x00000618,
812 	.hal_tcl_status_ring_base_lsb = 0x00000720,
815 	.hal_reo1_ring_base_lsb = 0x0000029c,
816 	.hal_reo1_ring_base_msb = 0x000002a0,
817 	.hal_reo1_ring_id = 0x000002a4,
818 	.hal_reo1_ring_misc = 0x000002ac,
819 	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
820 	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
821 	.hal_reo1_ring_producer_int_setup = 0x000002c0,
822 	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
823 	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
824 	.hal_reo1_ring_msi1_data = 0x000002ec,
825 	.hal_reo2_ring_base_lsb = 0x000002f4,
826 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
827 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
828 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
829 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
832 	.hal_reo1_ring_hp = 0x00003038,
833 	.hal_reo1_ring_tp = 0x0000303c,
834 	.hal_reo2_ring_hp = 0x00003040,
837 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
838 	.hal_reo_tcl_ring_hp = 0x00003058,
841 	.hal_reo_status_ring_base_lsb = 0x00000504,
842 	.hal_reo_status_hp = 0x00003070,
848 	.hal_tcl1_ring_base_lsb = 0x00000684,
849 	.hal_tcl1_ring_base_msb = 0x00000688,
850 	.hal_tcl1_ring_id = 0x0000068c,
851 	.hal_tcl1_ring_misc = 0x00000694,
852 	.hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
853 	.hal_tcl1_ring_tp_addr_msb = 0x000006a4,
854 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
855 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
856 	.hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
857 	.hal_tcl1_ring_msi1_base_msb = 0x000006d0,
858 	.hal_tcl1_ring_msi1_data = 0x000006d4,
859 	.hal_tcl2_ring_base_lsb = 0x000006dc,
860 	.hal_tcl_ring_base_lsb = 0x0000078c,
863 	.hal_tcl_status_ring_base_lsb = 0x00000894,
866 	.hal_reo1_ring_base_lsb = 0x00000244,
867 	.hal_reo1_ring_base_msb = 0x00000248,
868 	.hal_reo1_ring_id = 0x0000024c,
869 	.hal_reo1_ring_misc = 0x00000254,
870 	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
871 	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
872 	.hal_reo1_ring_producer_int_setup = 0x00000268,
873 	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
874 	.hal_reo1_ring_msi1_base_msb = 0x00000290,
875 	.hal_reo1_ring_msi1_data = 0x00000294,
876 	.hal_reo2_ring_base_lsb = 0x0000029c,
877 	.hal_reo1_aging_thresh_ix_0 = 0x0000050c,
878 	.hal_reo1_aging_thresh_ix_1 = 0x00000510,
879 	.hal_reo1_aging_thresh_ix_2 = 0x00000514,
880 	.hal_reo1_aging_thresh_ix_3 = 0x00000518,
883 	.hal_reo1_ring_hp = 0x00003030,
884 	.hal_reo1_ring_tp = 0x00003034,
885 	.hal_reo2_ring_hp = 0x00003038,
888 	.hal_reo_tcl_ring_base_lsb = 0x000003a4,
889 	.hal_reo_tcl_ring_hp = 0x00003050,
892 	.hal_reo_status_ring_base_lsb = 0x000004ac,
893 	.hal_reo_status_hp = 0x00003068,