ath/ath10k/rx_desc.h

13 	RX_ATTENTION_FLAGS_FIRST_MPDU          = BIT(0),
57  *		0.  The PPDU start status will only be valid when this bit
66  *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
213  *		ring 0.  Field is filled in by the RX_DMA.
229 	HTT_RX_MPDU_ENCRYPT_WEP40            = 0,
242 #define RX_MPDU_START_INFO0_PEER_IDX_MASK     0x000007ff
243 #define RX_MPDU_START_INFO0_PEER_IDX_LSB      0
244 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK      0x0fff0000
246 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
254 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
304  *		0: WEP40
315  *		Bits [31:0] of the PN number extracted from the IV field
316  *		WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0] is
319  *		WEPSeed[1], pn1}.  Only pn[47:0] is valid.
320  *		AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
321  *		pn0}.  Only pn[47:0] is valid.
322  *		WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
325  *		pn[47:0] are valid.
347 #define RX_MPDU_END_INFO0_RESERVED_0_MASK     0x00001fff
348 #define RX_MPDU_END_INFO0_RESERVED_0_LSB      0
349 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
401 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK    0x00003fff
402 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB     0
403 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK      0x000fc000
405 #define RX_MSDU_START_INFO0_RING_MASK_MASK      0x00f00000
407 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
410 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK    0x000000ff
411 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB     0
412 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK   0x00000300
414 #define RX_MSDU_START_INFO1_SA_IDX_MASK         0x07ff0000
423 #define RX_MSDU_START_INFO2_DA_IDX_MASK         0x000007ff
424 #define RX_MSDU_START_INFO2_DA_IDX_LSB          0
425 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000
433  *     - 0 bytes for no security
443 	RX_MSDU_DECAP_RAW = 0,
499  *		Only valid if tcp_prot or udp_prot is set.  The value 0
507  *		IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
508  *		protocol[7:0]}.
509  *		IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
510  *		next_header[7:0]}
511  *		UDP case: sort_port[15:0], dest_port[15:0]
512  *		TCP case: sort_port[15:0], dest_port[15:0],
513  *		{header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
514  *		{16'b0, urgent_ptr[15:0]}, all options except 32-bit
524  *		0: RAW: No decapsulation
550  *		the TCP payload is 0.
560 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
561 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB  0
577 #define RX_MSDU_END_INFO1_TCP_FLAG_MASK     0x000001ff
578 #define RX_MSDU_END_INFO1_TCP_FLAG_LSB      0
579 #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK   0x00001c00
581 #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK  0xffff0000
585 #define RX_MSDU_END_INFO2_DA_OFFSET_MASK    0x0000003f
586 #define RX_MSDU_END_INFO2_DA_OFFSET_LSB     0
587 #define RX_MSDU_END_INFO2_SA_OFFSET_MASK    0x00000fc0
589 #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK  0x0003f000
640  *		WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
663  *		have both first_mpdu and last_mpdu bits set to 0.
686 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY        0x04
687 #define HTT_RX_PPDU_START_PREAMBLE_HT            0x08
688 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF  0x09
689 #define HTT_RX_PPDU_START_PREAMBLE_VHT           0x0C
690 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
692 #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0)
694 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK    0x0000000f
695 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB     0
696 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK  0x0001ffe0
698 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK    0x00fc0000
700 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
705 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
706 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB  0
708 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
709 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB  0
712 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
713 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB  0
715 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
716 #define RX_PPDU_START_INFO5_SERVICE_LSB  0
740  *		RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
741  *		Value of 0x80 indicates invalid.
744  *		RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
745  *		Value of 0x80 indicates invalid.
748  *		RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
749  *		Value of 0x80 indicates invalid.
752  *		RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
753  *		Value of 0x80 indicates invalid.
757  *		Value of 0x80 indicates invalid.
761  *		Value of 0x80 indicates invalid.
765  *		Value of 0x80 indicates invalid.
769  *		Value of 0x80 indicates invalid.
773  *		Value of 0x80 indicates invalid.
777  *		Value of 0x80 indicates invalid.
781  *		Value of 0x80 indicates invalid.
785  *		Value of 0x80 indicates invalid.
789  *		Value of 0x80 indicates invalid.
793  *		Value of 0x80 indicates invalid.
797  *		Value of 0x80 indicates invalid.
801  *		Value of 0x80 indicates invalid.
805  *		bandwidths.  Value of 0x80 indicates invalid.
808  *		Reserved: HW should fill with 0, FW should ignore.
814  *		Reserved: HW should fill with 0, FW should ignore.
817  *		If l_sig_rate_select is 0:
818  *		0x8: OFDM 48 Mbps
819  *		0x9: OFDM 24 Mbps
820  *		0xA: OFDM 12 Mbps
821  *		0xB: OFDM 6 Mbps
822  *		0xC: OFDM 54 Mbps
823  *		0xD: OFDM 36 Mbps
824  *		0xE: OFDM 18 Mbps
825  *		0xF: OFDM 9 Mbps
827  *		0x8: CCK 11 Mbps long preamble
828  *		0x9: CCK 5.5 Mbps long preamble
829  *		0xA: CCK 2 Mbps long preamble
830  *		0xB: CCK 1 Mbps long preamble
831  *		0xC: CCK 11 Mbps short preamble
832  *		0xD: CCK 5.5 Mbps short preamble
833  *		0xE: CCK 2 Mbps short preamble
850  *		0x4: Legacy (OFDM/CCK)
851  *		0x8: HT
852  *		0x9: HT with TxBF
853  *		0xC: VHT
854  *		0xD: VHT with TxBF
855  *		0x80 - 0xFF: Reserved for special baseband data types such
859  *		If preamble_type == 0x8 or 0x9
861  *		If preamble_type == 0xC or 0xD
867  *		Reserved: HW should fill with 0, FW should ignore.
870  *		If preamble_type == 0x8 or 0x9
872  *		If preamble_type == 0xC or 0xD
882  *		Reserved: HW should fill with 0, FW should ignore.
886  *		0s since the BB does not plan on decoding VHT SIG-B.
889  *		Reserved: HW should fill with 0, FW should ignore.
893  *		packets will have service field of 0.
896  *		Reserved: HW should fill with 0, FW should ignore.
899 #define RX_PPDU_END_FLAGS_PHY_ERR             BIT(0)
903 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK     0x00ffffff
904 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB      0
908 #define RX_PPDU_END_INFO1_PEER_IDX_MASK       0x1ffc
910 #define RX_PPDU_END_INFO1_BB_DATA             BIT(0)
944 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff
945 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB  0
946 #define RX_PPDU_END_RTT_UNUSED_MASK            0x7f000000
960 #define RX_PKT_END_INFO0_RX_SUCCESS              BIT(0)
967 #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK       0x0001ffff
968 #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB        0
969 #define RX_LOCATION_INFO_FAC_STATUS_MASK         0x000c0000
971 #define RX_LOCATION_INFO_PKT_BW_MASK             0x00700000
973 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000
993 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK		0x00003fff
994 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB		0
995 #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK		0x1fff8000
997 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK	0xc0000000
1002 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK	0x0000000c
1004 #define RX_LOCATION_INFO1_PKT_BW_MASK			0x00000030
1006 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK		0x0000ff00
1008 #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK		0x000f0000
1010 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK		0x00300000
1012 #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK		0x07c00000
1014 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK	0x18000000
1016 #define RX_LOCATION_INFO1_RTT_CFR_STATUS		BIT(0)
1068 	RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP            = BIT(0),
1089 #define RX_PPDU_END_RX_TIMING_OFFSET_MASK          0x00000fff
1090 #define RX_PPDU_END_RX_TIMING_OFFSET_LSB           0
1092 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK        0x00ffffff
1093 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB         0
1149  *		EVM for pilot 0.  Contain EVM for streams: 0, 1, 2 and 3.
1152  *		EVM for pilot 1.  Contain EVM for streams: 0, 1, 2 and 3.
1155  *		EVM for pilot 2.  Contain EVM for streams: 0, 1, 2 and 3.
1158  *		EVM for pilot 3.  Contain EVM for streams: 0, 1, 2 and 3.
1161  *		EVM for pilot 4.  Contain EVM for streams: 0, 1, 2 and 3.
1164  *		EVM for pilot 5.  Contain EVM for streams: 0, 1, 2 and 3.
1167  *		EVM for pilot 6.  Contain EVM for streams: 0, 1, 2 and 3.
1170  *		EVM for pilot 7.  Contain EVM for streams: 0, 1, 2 and 3.
1173  *		EVM for pilot 8.  Contain EVM for streams: 0, 1, 2 and 3.
1176  *		EVM for pilot 9.  Contain EVM for streams: 0, 1, 2 and 3.
1179  *		EVM for pilot 10.  Contain EVM for streams: 0, 1, 2 and 3.
1182  *		EVM for pilot 11.  Contain EVM for streams: 0, 1, 2 and 3.
1185  *		EVM for pilot 12.  Contain EVM for streams: 0, 1, 2 and 3.
1188  *		EVM for pilot 13.  Contain EVM for streams: 0, 1, 2 and 3.
1191  *		EVM for pilot 14.  Contain EVM for streams: 0, 1, 2 and 3.
1194  *		EVM for pilot 15.  Contain EVM for streams: 0, 1, 2 and 3.
1212  *		nsec.  The value starts at 0 and increments to 79 and
1213  *		returns to 0 and repeats.  This information is valid for
1231  *		Reserved: HW should fill with 0, FW should ignore.
1248  *		Reserved: HW should fill with 0, FW should ignore.
1252  *		PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
1257  *		Reserved: HW should fill with 0, FW should ignore.
1263  *		to 0.
1266 #define FW_RX_DESC_INFO0_DISCARD  BIT(0)
1269 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0
1276 #define FW_RX_DESC_FLAGS_FIRST_MSDU (1 << 0)