net/vmxnet3/vmxnet3_defs.h

4  * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-drivers@vmware.com
57 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
104  *	Little Endian layout of bitfields -
110  *	Big Endian layout of bitfields -
116  *	Thus, le32_to_cpu on the dword will allow the big endian driver to read
118  *	bit fields written by big endian driver to format required by device.
370 /* # of tx desc needed for a tx buffer size */
371 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
374 /* max # of tx descs for a non-tso pkt */
378 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
385 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
389 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
393 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
397 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
414  VMXNET3_ERR_NOEOP        = 0x80000000,  /* cannot find the EOP desc of a pkt */
443 	u32		gosBits:2;    /* 32-bit or 64-bit? */
445 	u32		gosBits:2;     /* 32-bit or 64-bit? */
477 	__le32		queueDescLen; /* queue desc. table len in bytes */
492 	__le32		txRingSize;   /* # of tx desc */
493 	__le32		dataRingSize; /* # of data desc */
494 	__le32		compRingSize; /* # of comp desc */
508 	__le32		rxRingSize[2];   /* # of rx desc */
509 	__le32		compRingSize;    /* # of rx comp desc */
713 	/* read-only region for device, read by dev in response to a SET cmd */