4  * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
8  * Free Software Foundation; version 2 of the License and no later version.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-drivers@vmware.com
51 	VMXNET3_REG_RXPROD2	= 0xA00	 /* Rx Producer Index for ring 2 */
57 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
104  *	Little Endian layout of bitfields -
106  *	Byte 1 :	oco gen 13.len.8
107  *	Byte 2 : 	5.msscof.0 ext1  dtype
110  *	Big Endian layout of bitfields -
113  *	Byte 2 :	oco gen 13.len.8
129 	u32 gen:1;      /* generation bit */  member
133 	u32 gen:1;      /* generation bit */  member
146 	u32 om:2;       /* offload mode */
150 	u32 om:2;       /* offload mode */
162 #define VMXNET3_OM_CSUM         2
170 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
200 	u32		gen:1;        /* generation bit */  member
207 	u32		gen:1;        /* Generation bit */  member
217 	u32		gen:1;        /* Generation bit */  member
240 	u32		ext1:2;
244 	u32		ext1:2;
269 	u32		gen:1;        /* generation bit */  member
291 	u32		gen:1;        /* generation bit */  member
302 	u32		gen:1;        /* generation bit */  member
324 	u32		gen:1;        /* generation bit */  member
347 	VMXNET3_RCD_RSS_TYPE_TCPIPV4  = 2,
355 	__le64				qword[2];
371 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
374 /* max # of tx descs for a non-tso pkt */
378 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
385 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
389 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
393 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
397 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
432 	VMXNET3_GOS_BITS_64     = 2,
443 	u32		gosBits:2;    /* 32-bit or 64-bit? */
445 	u32		gosBits:2;     /* 32-bit or 64-bit? */
504 	__le64		rxRingBasePA[2];
508 	__le32		rxRingSize[2];   /* # of rx desc */
521 	VMXNET3_IMM_LAZY   = 2
527 	VMXNET3_IT_MSI  = 2,
547 	__le32		reserved[2];
655 	VMXNET3_COALESCE_STATIC     = 2,
709 	__le64					data[2];
713 	/* read-only region for device, read by dev in response to a SET cmd */
742 #define VMXNET3_ECR_LINK        (1 << 2)
746 /* flip the gen bit of a ring */
747 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)  argument
749 /* only use this if moving the idx won't affect the gen bit */