1 // SPDX-License-Identifier: GPL-2.0+
10  * phy_speed_to_str - Return a string representing the PHY link speed
55 		return "Unsupported (update phy-core.c)";  in phy_speed_to_str()
61  * phy_duplex_to_str - Return string describing the duplex
70 		return "Full";  in phy_duplex_to_str()
73 	return "Unsupported (update phy-core.c)";  in phy_duplex_to_str()
79  * - iow, descending speed. */
82 			       .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
86 	PHY_SETTING( 400000, FULL, 400000baseCR8_Full		),
87 	PHY_SETTING( 400000, FULL, 400000baseKR8_Full		),
88 	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	),
89 	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		),
90 	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		),
91 	PHY_SETTING( 400000, FULL, 400000baseCR4_Full		),
92 	PHY_SETTING( 400000, FULL, 400000baseKR4_Full		),
93 	PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full	),
94 	PHY_SETTING( 400000, FULL, 400000baseDR4_Full		),
95 	PHY_SETTING( 400000, FULL, 400000baseSR4_Full		),
97 	PHY_SETTING( 200000, FULL, 200000baseCR4_Full		),
98 	PHY_SETTING( 200000, FULL, 200000baseKR4_Full		),
99 	PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full	),
100 	PHY_SETTING( 200000, FULL, 200000baseDR4_Full		),
101 	PHY_SETTING( 200000, FULL, 200000baseSR4_Full		),
102 	PHY_SETTING( 200000, FULL, 200000baseCR2_Full		),
103 	PHY_SETTING( 200000, FULL, 200000baseKR2_Full		),
104 	PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full	),
105 	PHY_SETTING( 200000, FULL, 200000baseDR2_Full		),
106 	PHY_SETTING( 200000, FULL, 200000baseSR2_Full		),
108 	PHY_SETTING( 100000, FULL, 100000baseCR4_Full		),
109 	PHY_SETTING( 100000, FULL, 100000baseKR4_Full		),
110 	PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full	),
111 	PHY_SETTING( 100000, FULL, 100000baseSR4_Full		),
112 	PHY_SETTING( 100000, FULL, 100000baseCR2_Full		),
113 	PHY_SETTING( 100000, FULL, 100000baseKR2_Full		),
114 	PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full	),
115 	PHY_SETTING( 100000, FULL, 100000baseDR2_Full		),
116 	PHY_SETTING( 100000, FULL, 100000baseSR2_Full		),
117 	PHY_SETTING( 100000, FULL, 100000baseCR_Full		),
118 	PHY_SETTING( 100000, FULL, 100000baseKR_Full		),
119 	PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full	),
120 	PHY_SETTING( 100000, FULL, 100000baseDR_Full		),
121 	PHY_SETTING( 100000, FULL, 100000baseSR_Full		),
123 	PHY_SETTING(  56000, FULL,  56000baseCR4_Full	  	),
124 	PHY_SETTING(  56000, FULL,  56000baseKR4_Full	  	),
125 	PHY_SETTING(  56000, FULL,  56000baseLR4_Full	  	),
126 	PHY_SETTING(  56000, FULL,  56000baseSR4_Full	  	),
128 	PHY_SETTING(  50000, FULL,  50000baseCR2_Full		),
129 	PHY_SETTING(  50000, FULL,  50000baseKR2_Full		),
130 	PHY_SETTING(  50000, FULL,  50000baseSR2_Full		),
131 	PHY_SETTING(  50000, FULL,  50000baseCR_Full		),
132 	PHY_SETTING(  50000, FULL,  50000baseKR_Full		),
133 	PHY_SETTING(  50000, FULL,  50000baseLR_ER_FR_Full	),
134 	PHY_SETTING(  50000, FULL,  50000baseDR_Full		),
135 	PHY_SETTING(  50000, FULL,  50000baseSR_Full		),
137 	PHY_SETTING(  40000, FULL,  40000baseCR4_Full		),
138 	PHY_SETTING(  40000, FULL,  40000baseKR4_Full		),
139 	PHY_SETTING(  40000, FULL,  40000baseLR4_Full		),
140 	PHY_SETTING(  40000, FULL,  40000baseSR4_Full		),
142 	PHY_SETTING(  25000, FULL,  25000baseCR_Full		),
143 	PHY_SETTING(  25000, FULL,  25000baseKR_Full		),
144 	PHY_SETTING(  25000, FULL,  25000baseSR_Full		),
146 	PHY_SETTING(  20000, FULL,  20000baseKR2_Full		),
147 	PHY_SETTING(  20000, FULL,  20000baseMLD2_Full		),
149 	PHY_SETTING(  10000, FULL,  10000baseCR_Full		),
150 	PHY_SETTING(  10000, FULL,  10000baseER_Full		),
151 	PHY_SETTING(  10000, FULL,  10000baseKR_Full		),
152 	PHY_SETTING(  10000, FULL,  10000baseKX4_Full		),
153 	PHY_SETTING(  10000, FULL,  10000baseLR_Full		),
154 	PHY_SETTING(  10000, FULL,  10000baseLRM_Full		),
155 	PHY_SETTING(  10000, FULL,  10000baseR_FEC		),
156 	PHY_SETTING(  10000, FULL,  10000baseSR_Full		),
157 	PHY_SETTING(  10000, FULL,  10000baseT_Full		),
159 	PHY_SETTING(   5000, FULL,   5000baseT_Full		),
161 	PHY_SETTING(   2500, FULL,   2500baseT_Full		),
162 	PHY_SETTING(   2500, FULL,   2500baseX_Full		),
164 	PHY_SETTING(   1000, FULL,   1000baseKX_Full		),
165 	PHY_SETTING(   1000, FULL,   1000baseT_Full		),
167 	PHY_SETTING(   1000, FULL,   1000baseT1_Full		),
168 	PHY_SETTING(   1000, FULL,   1000baseX_Full		),
170 	PHY_SETTING(    100, FULL,    100baseT_Full		),
171 	PHY_SETTING(    100, FULL,    100baseT1_Full		),
174 	PHY_SETTING(    100, FULL,    100baseFX_Full		),
176 	PHY_SETTING(     10, FULL,     10baseT_Full		),
182  * phy_lookup_setting - lookup a PHY setting
205 		if (p->bit < __ETHTOOL_LINK_MODE_MASK_NBITS &&  in phy_lookup_setting()
206 		    test_bit(p->bit, mask)) {  in phy_lookup_setting()
208 			if (p->speed == speed && p->duplex == duplex) {  in phy_lookup_setting()
213 				if (!match && p->speed <= speed)  in phy_lookup_setting()
217 				if (p->speed < speed)  in phy_lookup_setting()
237 		if (settings[i].bit < __ETHTOOL_LINK_MODE_MASK_NBITS &&  in phy_speeds()
238 		    test_bit(settings[i].bit, mask) &&  in phy_speeds()
239 		    (count == 0 || speeds[count - 1] != settings[i].speed))  in phy_speeds()
251 		if (p->speed > max_speed)  in __set_linkmode_max_speed()
252 			linkmode_clear_bit(p->bit, addr);  in __set_linkmode_max_speed()
262 	return __set_linkmode_max_speed(max_speed, phydev->supported);  in __set_phy_supported()
266  * phy_set_max_speed - Set the maximum speed the PHY should support
291 	struct device_node *node = phydev->mdio.dev.of_node;  in of_set_phy_supported()
300 	if (!of_property_read_u32(node, "max-speed", &max_speed))  in of_set_phy_supported()
306 	struct device_node *node = phydev->mdio.dev.of_node;  in of_set_phy_eee_broken()
315 	if (of_property_read_bool(node, "eee-broken-100tx"))  in of_set_phy_eee_broken()
317 	if (of_property_read_bool(node, "eee-broken-1000t"))  in of_set_phy_eee_broken()
319 	if (of_property_read_bool(node, "eee-broken-10gt"))  in of_set_phy_eee_broken()
321 	if (of_property_read_bool(node, "eee-broken-1000kx"))  in of_set_phy_eee_broken()
323 	if (of_property_read_bool(node, "eee-broken-10gkx4"))  in of_set_phy_eee_broken()
325 	if (of_property_read_bool(node, "eee-broken-10gkr"))  in of_set_phy_eee_broken()
328 	phydev->eee_broken_modes = broken;  in of_set_phy_eee_broken()
332  * phy_resolve_aneg_pause - Determine pause autoneg results
343 	if (phydev->duplex == DUPLEX_FULL) {  in phy_resolve_aneg_pause()
344 		phydev->pause = linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,  in phy_resolve_aneg_pause()
345 						  phydev->lp_advertising);  in phy_resolve_aneg_pause()
346 		phydev->asym_pause = linkmode_test_bit(  in phy_resolve_aneg_pause()
348 			phydev->lp_advertising);  in phy_resolve_aneg_pause()
354  * phy_resolve_aneg_linkmode - resolve the advertisements into PHY settings
358  * speed and duplex. If full duplex was negotiated, extract the pause mode
366 	linkmode_and(common, phydev->lp_advertising, phydev->advertising);  in phy_resolve_aneg_linkmode()
369 		if (test_bit(settings[i].bit, common)) {  in phy_resolve_aneg_linkmode()
370 			phydev->speed = settings[i].speed;  in phy_resolve_aneg_linkmode()
371 			phydev->duplex = settings[i].duplex;  in phy_resolve_aneg_linkmode()
380  * phy_check_downshift - check whether downshift occurred
386  * read_status callback and sets phydev->speed to the actual link speed.
393 	phydev->downshifted_rate = 0;  in phy_check_downshift()
395 	if (phydev->autoneg == AUTONEG_DISABLE ||  in phy_check_downshift()
396 	    phydev->speed == SPEED_UNKNOWN)  in phy_check_downshift()
399 	linkmode_and(common, phydev->lp_advertising, phydev->advertising);  in phy_check_downshift()
402 		if (test_bit(settings[i].bit, common)) {  in phy_check_downshift()
407 	if (speed == SPEED_UNKNOWN || phydev->speed >= speed)  in phy_check_downshift()
411 		    phy_speed_to_str(speed), phy_speed_to_str(phydev->speed));  in phy_check_downshift()
413 	phydev->downshifted_rate = 1;  in phy_check_downshift()
422 	linkmode_and(common, phydev->lp_advertising, phydev->advertising);  in phy_resolve_min_speed()
424 	while (--i >= 0) {  in phy_resolve_min_speed()
425 		if (test_bit(settings[i].bit, common)) {  in phy_resolve_min_speed()
440 		return -EINVAL;  in phy_speed_down_core()
442 	return __set_linkmode_max_speed(min_common_speed, phydev->advertising);  in phy_speed_down_core()
460  * __phy_read_mmd - Convenience function for reading a register
473 		return -EINVAL;  in __phy_read_mmd()
475 	if (phydev->drv && phydev->drv->read_mmd) {  in __phy_read_mmd()
476 		val = phydev->drv->read_mmd(phydev, devad, regnum);  in __phy_read_mmd()
477 	} else if (phydev->is_c45) {  in __phy_read_mmd()
478 		val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr,  in __phy_read_mmd()
481 		struct mii_bus *bus = phydev->mdio.bus;  in __phy_read_mmd()
482 		int phy_addr = phydev->mdio.addr;  in __phy_read_mmd()
494  * phy_read_mmd - Convenience function for reading a register
515  * __phy_write_mmd - Convenience function for writing a register
529 		return -EINVAL;  in __phy_write_mmd()
531 	if (phydev->drv && phydev->drv->write_mmd) {  in __phy_write_mmd()
532 		ret = phydev->drv->write_mmd(phydev, devad, regnum, val);  in __phy_write_mmd()
533 	} else if (phydev->is_c45) {  in __phy_write_mmd()
534 		ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr,  in __phy_write_mmd()
537 		struct mii_bus *bus = phydev->mdio.bus;  in __phy_write_mmd()
538 		int phy_addr = phydev->mdio.addr;  in __phy_write_mmd()
552  * phy_write_mmd - Convenience function for writing a register
574  * phy_modify_changed - Function for modifying a PHY register
577  * @mask: bit mask of bits to clear
599  * __phy_modify - Convenience function for modifying a PHY register
602  * @mask: bit mask of bits to clear
620  * phy_modify - Convenience function for modifying a given PHY register
623  * @mask: bit mask of bits to clear
643  * __phy_modify_mmd_changed - Function for modifying a register on MMD
647  * @mask: bit mask of bits to clear
675  * phy_modify_mmd_changed - Function for modifying a register on MMD
679  * @mask: bit mask of bits to clear
702  * __phy_modify_mmd - Convenience function for modifying a register on MMD
706  * @mask: bit mask of bits to clear
725  * phy_modify_mmd - Convenience function for modifying a register on MMD
729  * @mask: bit mask of bits to clear
751 …if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n…  in __phy_read_page()
752 		return -EOPNOTSUPP;  in __phy_read_page()
754 	return phydev->drv->read_page(phydev);  in __phy_read_page()
759 …if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?…  in __phy_write_page()
760 		return -EOPNOTSUPP;  in __phy_write_page()
762 	return phydev->drv->write_page(phydev, page);  in __phy_write_page()
766  * phy_save_page() - take the bus lock and save the current page
781  * phy_select_page() - take the bus lock, save the current page, and set a page
810  * phy_restore_page() - restore the page register and release the bus lock
849  * phy_read_paged() - Convenience function for reading a paged register
869  * phy_write_paged() - Convenience function for writing a paged register
890  * phy_modify_paged_changed() - Function for modifying a paged register
894  * @mask: bit mask of bits to clear
895  * @set: bit mask of bits to set
913  * phy_modify_paged() - Convenience function for modifying a paged register
917  * @mask: bit mask of bits to clear
918  * @set: bit mask of bits to set