Lines Matching full:phydev
110 static int vsc85xx_phy_read_page(struct phy_device *phydev) in vsc85xx_phy_read_page() argument
112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); in vsc85xx_phy_read_page()
115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) in vsc85xx_phy_write_page() argument
117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_write_page()
120 static int vsc85xx_get_sset_count(struct phy_device *phydev) in vsc85xx_get_sset_count() argument
122 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()
130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) in vsc85xx_get_strings() argument
132 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()
143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) in vsc85xx_get_stat() argument
145 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()
148 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()
159 static void vsc85xx_get_stats(struct phy_device *phydev, in vsc85xx_get_stats() argument
162 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stats()
169 data[i] = vsc85xx_get_stat(phydev, i); in vsc85xx_get_stats()
172 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
179 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
184 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_mdix_set()
234 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_get()
255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_set()
273 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
281 u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
283 mutex_lock(&phydev->lock); in vsc85xx_wol_set()
284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
286 rc = phy_restore_page(phydev, rc, rc); in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
347 mutex_unlock(&phydev->lock); in vsc85xx_wol_set()
352 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
361 mutex_lock(&phydev->lock); in vsc85xx_wol_get()
362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
382 mutex_unlock(&phydev->lock); in vsc85xx_wol_get()
386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
390 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
416 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_mode_get()
417 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
428 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, in vsc85xx_dt_led_modes_get() argument
452 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_modes_get()
461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, in vsc85xx_dt_led_modes_get()
471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
475 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_edge_rate_cntl_set()
479 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
484 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
490 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
515 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
518 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, in vsc85xx_rgmii_set_skews() argument
539 mutex_lock(&phydev->lock); in vsc85xx_rgmii_set_skews()
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || in vsc85xx_rgmii_set_skews()
542 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_rgmii_set_skews()
544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in vsc85xx_rgmii_set_skews()
545 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_rgmii_set_skews()
548 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_rgmii_set_skews()
553 mutex_unlock(&phydev->lock); in vsc85xx_rgmii_set_skews()
558 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
562 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
564 if (phy_interface_mode_is_rgmii(phydev->interface)) { in vsc85xx_default_config()
565 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL, in vsc85xx_default_config()
575 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
580 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
586 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
592 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc85xx_tr_write() argument
601 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc85xx_tr_write()
602 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
603 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc85xx_tr_write()
606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) in vsc8531_pre_init_seq_set() argument
618 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, in vsc8531_pre_init_seq_set()
623 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
636 mutex_lock(&phydev->lock); in vsc8531_pre_init_seq_set()
637 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc8531_pre_init_seq_set()
642 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); in vsc8531_pre_init_seq_set()
645 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc8531_pre_init_seq_set()
646 mutex_unlock(&phydev->lock); in vsc8531_pre_init_seq_set()
651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) in vsc85xx_eee_init_seq_set() argument
676 mutex_lock(&phydev->lock); in vsc85xx_eee_init_seq_set()
677 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc85xx_eee_init_seq_set()
682 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); in vsc85xx_eee_init_seq_set()
685 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc85xx_eee_init_seq_set()
686 mutex_unlock(&phydev->lock); in vsc85xx_eee_init_seq_set()
691 /* phydev->bus->mdio_lock should be locked when using this function */
692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_base_write() argument
694 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_write()
695 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_write()
699 return __phy_package_write(phydev, regnum, val); in phy_base_write()
702 /* phydev->bus->mdio_lock should be locked when using this function */
703 static int phy_base_read(struct phy_device *phydev, u32 regnum) in phy_base_read() argument
705 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_read()
706 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_read()
710 return __phy_package_read(phydev, regnum); in phy_base_read()
714 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc8584_csr_write() argument
716 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc8584_csr_write()
717 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
718 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc8584_csr_write()
722 static int vsc8584_cmd(struct phy_device *phydev, u16 val) in vsc8584_cmd() argument
727 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
730 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); in vsc8584_cmd()
734 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); in vsc8584_cmd()
739 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_cmd()
751 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, in vsc8584_micro_deassert_reset() argument
756 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
768 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_micro_deassert_reset()
774 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
776 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
778 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_deassert_reset()
784 static int vsc8584_micro_assert_reset(struct phy_device *phydev) in vsc8584_micro_assert_reset() argument
789 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
793 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
796 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
798 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
800 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
801 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
803 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
805 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
807 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
809 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
811 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
813 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | in vsc8584_micro_assert_reset()
817 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
819 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
821 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_assert_reset()
827 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, in vsc8584_get_fw_crc() argument
832 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
834 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
835 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); in vsc8584_get_fw_crc()
838 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
842 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
844 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
847 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_fw_crc()
853 static int vsc8584_patch_fw(struct phy_device *phydev, in vsc8584_patch_fw() argument
858 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_patch_fw()
860 dev_err(&phydev->mdio.dev, in vsc8584_patch_fw()
865 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
871 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | in vsc8584_patch_fw()
874 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | in vsc8584_patch_fw()
876 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
879 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
883 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
885 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_patch_fw()
891 static bool vsc8574_is_serdes_init(struct phy_device *phydev) in vsc8574_is_serdes_init() argument
896 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
899 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
905 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
911 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
917 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
926 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_is_serdes_init()
932 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
998 struct device *dev = &phydev->mdio.dev; in vsc8574_config_pre_init()
1005 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1008 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1010 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1012 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1019 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1021 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1023 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1024 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1025 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1026 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1028 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1030 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1032 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1035 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8574_config_pre_init()
1037 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8574_config_pre_init()
1039 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1041 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1044 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8574_config_pre_init()
1046 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1048 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1050 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1052 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1055 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1057 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1067 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1074 serdes_init = vsc8574_is_serdes_init(phydev); in vsc8574_config_pre_init()
1077 ret = vsc8584_micro_assert_reset(phydev); in vsc8574_config_pre_init()
1090 if (vsc8584_patch_fw(phydev, fw)) in vsc8574_config_pre_init()
1096 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1099 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1100 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1101 phy_base_write(phydev, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
1104 vsc8584_micro_deassert_reset(phydev, false); in vsc8574_config_pre_init()
1109 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1120 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1123 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
1127 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1135 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
1167 struct device *dev = &phydev->mdio.dev; in vsc8584_config_pre_init()
1172 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1175 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1177 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1179 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1181 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
1183 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
1190 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); in vsc8584_config_pre_init()
1192 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1194 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1196 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1198 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1200 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1202 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1204 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1206 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); in vsc8584_config_pre_init()
1209 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); in vsc8584_config_pre_init()
1211 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1214 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8584_config_pre_init()
1216 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8584_config_pre_init()
1218 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1220 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1223 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8584_config_pre_init()
1225 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1227 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1229 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1231 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1234 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1236 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1246 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1254 if (vsc8584_patch_fw(phydev, fw)) in vsc8584_config_pre_init()
1259 vsc8584_micro_deassert_reset(phydev, false); in vsc8584_config_pre_init()
1262 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1272 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_config_pre_init()
1276 vsc8584_micro_deassert_reset(phydev, true); in vsc8584_config_pre_init()
1279 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1286 static void vsc8584_get_base_addr(struct phy_device *phydev) in vsc8584_get_base_addr() argument
1288 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_get_base_addr()
1291 phy_lock_mdio_bus(phydev); in vsc8584_get_base_addr()
1292 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_base_addr()
1294 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8584_get_base_addr()
1297 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc8584_get_base_addr()
1299 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_base_addr()
1300 phy_unlock_mdio_bus(phydev); in vsc8584_get_base_addr()
1306 vsc8531->ts_base_addr = phydev->mdio.addr; in vsc8584_get_base_addr()
1310 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8584_get_base_addr()
1316 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8584_get_base_addr()
1326 static int vsc8584_config_init(struct phy_device *phydev) in vsc8584_config_init() argument
1328 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_init()
1332 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8584_config_init()
1334 phy_lock_mdio_bus(phydev); in vsc8584_config_init()
1349 if (phy_package_init_once(phydev)) { in vsc8584_config_init()
1354 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1356 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_config_init()
1361 ret = vsc8574_config_pre_init(phydev); in vsc8584_config_init()
1367 ret = vsc8584_config_pre_init(phydev); in vsc8584_config_init()
1378 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1383 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_init()
1385 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8584_config_init()
1387 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8584_config_init()
1389 } else if (phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1396 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8584_config_init()
1400 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1405 if (!phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1408 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_init()
1413 ret = vsc8584_cmd(phydev, val); in vsc8584_config_init()
1421 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1430 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1438 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1440 ret = vsc8584_macsec_init(phydev); in vsc8584_config_init()
1444 ret = vsc8584_ptp_init(phydev); in vsc8584_config_init()
1448 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc8584_config_init()
1452 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); in vsc8584_config_init()
1456 if (phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1457 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL, in vsc8584_config_init()
1464 ret = genphy_soft_reset(phydev); in vsc8584_config_init()
1469 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8584_config_init()
1477 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1481 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) in vsc8584_handle_interrupt() argument
1486 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_handle_interrupt()
1493 ret = vsc8584_handle_ts_interrupt(phydev); in vsc8584_handle_interrupt()
1498 vsc8584_handle_macsec_interrupt(phydev); in vsc8584_handle_interrupt()
1501 phy_mac_interrupt(phydev); in vsc8584_handle_interrupt()
1506 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
1509 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
1511 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
1515 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
1519 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
1523 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; in vsc85xx_config_init()
1526 rc = vsc8531_pre_init_seq_set(phydev); in vsc85xx_config_init()
1531 rc = vsc85xx_eee_init_seq_set(phydev); in vsc85xx_config_init()
1536 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc85xx_config_init()
1544 static int vsc8584_did_interrupt(struct phy_device *phydev) in vsc8584_did_interrupt() argument
1548 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc8584_did_interrupt()
1549 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_did_interrupt()
1554 static int vsc8514_config_pre_init(struct phy_device *phydev) in vsc8514_config_pre_init() argument
1585 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1588 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1590 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1592 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1594 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1596 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1598 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8514_config_pre_init()
1601 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8514_config_pre_init()
1603 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1605 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1607 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1609 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1611 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1613 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1618 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, in vsc85xx_csr_ctrl_phy_read() argument
1624 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_ctrl_phy_read()
1634 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_ctrl_phy_read()
1638 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_ctrl_phy_read()
1647 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_ctrl_phy_read()
1655 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); in vsc85xx_csr_ctrl_phy_read()
1658 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); in vsc85xx_csr_ctrl_phy_read()
1660 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_ctrl_phy_read()
1666 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev, in vsc85xx_csr_ctrl_phy_write() argument
1671 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_ctrl_phy_write()
1681 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_ctrl_phy_write()
1685 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); in vsc85xx_csr_ctrl_phy_write()
1688 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); in vsc85xx_csr_ctrl_phy_write()
1691 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_ctrl_phy_write()
1700 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_ctrl_phy_write()
1707 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_ctrl_phy_write()
1713 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, in __phy_write_mcb_s6g() argument
1720 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg, in __phy_write_mcb_s6g()
1728 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); in __phy_write_mcb_s6g()
1742 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_update_mcb_s6g() argument
1744 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); in phy_update_mcb_s6g()
1748 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_commit_mcb_s6g() argument
1750 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); in phy_commit_mcb_s6g()
1753 static int vsc8514_config_init(struct phy_device *phydev) in vsc8514_config_init() argument
1755 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8514_config_init()
1761 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8514_config_init()
1763 phy_lock_mdio_bus(phydev); in vsc8514_config_init()
1776 if (phy_package_init_once(phydev)) in vsc8514_config_init()
1777 vsc8514_config_pre_init(phydev); in vsc8514_config_init()
1779 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
1784 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8514_config_init()
1788 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8514_config_init()
1792 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
1797 ret = vsc8584_cmd(phydev, in vsc8514_config_init()
1805 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1807 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1809 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1814 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1816 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1825 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1836 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1842 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1847 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); in vsc8514_config_init()
1852 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
1854 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1857 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1864 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1869 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1874 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1879 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
1881 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1884 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1891 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1895 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1897 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()
1903 ret = genphy_soft_reset(phydev); in vsc8514_config_init()
1909 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8514_config_init()
1917 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1921 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
1925 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
1926 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
1931 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
1935 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
1936 vsc8584_config_macsec_intr(phydev); in vsc85xx_config_intr()
1937 vsc8584_config_ts_intr(phydev); in vsc85xx_config_intr()
1939 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
1942 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
1945 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
1951 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
1955 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
1959 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
1962 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
1966 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
1970 return genphy_read_status(phydev); in vsc85xx_read_status()
1973 static int vsc8514_probe(struct phy_device *phydev) in vsc8514_probe() argument
1980 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8514_probe()
1984 phydev->priv = vsc8531; in vsc8514_probe()
1986 vsc8584_get_base_addr(phydev); in vsc8514_probe()
1987 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8514_probe()
1994 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8514_probe()
1999 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8514_probe()
2002 static int vsc8574_probe(struct phy_device *phydev) in vsc8574_probe() argument
2009 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8574_probe()
2013 phydev->priv = vsc8531; in vsc8574_probe()
2015 vsc8584_get_base_addr(phydev); in vsc8574_probe()
2016 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8574_probe()
2023 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8574_probe()
2028 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8574_probe()
2031 static int vsc8584_probe(struct phy_device *phydev) in vsc8584_probe() argument
2039 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { in vsc8584_probe()
2040 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); in vsc8584_probe()
2044 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8584_probe()
2048 phydev->priv = vsc8531; in vsc8584_probe()
2050 vsc8584_get_base_addr(phydev); in vsc8584_probe()
2051 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, in vsc8584_probe()
2058 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8584_probe()
2063 if (phy_package_probe_once(phydev)) { in vsc8584_probe()
2064 ret = vsc8584_ptp_probe_once(phydev); in vsc8584_probe()
2069 ret = vsc8584_ptp_probe(phydev); in vsc8584_probe()
2073 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8584_probe()
2076 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
2083 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
2087 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
2091 phydev->priv = vsc8531; in vsc85xx_probe()
2098 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc85xx_probe()
2103 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc85xx_probe()