Lines Matching full:phydev
46 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_d0_afe_config_init() argument
49 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
52 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
55 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
58 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
61 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
64 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
67 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
72 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
75 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
78 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
81 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_d0_afe_config_init()
86 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_e0_plus_afe_config_init() argument
89 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
92 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
95 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
100 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
103 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
106 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
109 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_e0_plus_afe_config_init()
114 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_a0_patch_afe_config_init() argument
117 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
120 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
123 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
126 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
129 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
132 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
134 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_a0_patch_afe_config_init()
139 static int bcm7xxx_28nm_config_init(struct phy_device *phydev) in bcm7xxx_28nm_config_init() argument
141 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); in bcm7xxx_28nm_config_init()
142 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); in bcm7xxx_28nm_config_init()
150 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_config_init()
153 phydev_name(phydev), phydev->drv->name, rev, patch); in bcm7xxx_28nm_config_init()
160 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_config_init()
165 ret = bcm_phy_28nm_a0b0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
168 ret = bcm7xxx_28nm_d0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
174 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
177 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
186 ret = bcm_phy_enable_jumbo(phydev); in bcm7xxx_28nm_config_init()
190 ret = bcm_phy_downshift_get(phydev, &count); in bcm7xxx_28nm_config_init()
195 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_config_init()
199 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_28nm_config_init()
202 static int bcm7xxx_28nm_resume(struct phy_device *phydev) in bcm7xxx_28nm_resume() argument
207 ret = bcm7xxx_28nm_config_init(phydev); in bcm7xxx_28nm_resume()
216 return genphy_config_aneg(phydev); in bcm7xxx_28nm_resume()
238 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_01_afe_config_init() argument
243 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_01_afe_config_init()
249 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
254 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
258 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
264 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
268 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
275 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
284 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_apd_enable() argument
289 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, in bcm7xxx_28nm_ephy_apd_enable()
295 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in bcm7xxx_28nm_ephy_apd_enable()
301 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
309 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_eee_enable() argument
314 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_eee_enable()
320 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
324 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
330 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
334 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
339 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
343 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
349 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
353 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
360 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
366 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
372 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_config_init() argument
374 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_ephy_config_init()
378 phydev_name(phydev), phydev->drv->name, rev); in bcm7xxx_28nm_ephy_config_init()
385 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_ephy_config_init()
389 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev); in bcm7xxx_28nm_ephy_config_init()
394 ret = bcm7xxx_28nm_ephy_eee_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
398 return bcm7xxx_28nm_ephy_apd_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
401 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_28nm_ephy_resume() argument
406 ret = bcm7xxx_28nm_ephy_config_init(phydev); in bcm7xxx_28nm_ephy_resume()
410 return genphy_config_aneg(phydev); in bcm7xxx_28nm_ephy_resume()
413 static int bcm7xxx_config_init(struct phy_device *phydev) in bcm7xxx_config_init() argument
418 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO); in bcm7xxx_config_init()
419 phy_read(phydev, MII_BCM7XXX_AUX_MODE); in bcm7xxx_config_init()
422 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_config_init()
428 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
432 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
434 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
437 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
447 static int bcm7xxx_suspend(struct phy_device *phydev) in bcm7xxx_suspend() argument
464 ret = phy_write(phydev, in bcm7xxx_suspend()
474 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev, in bcm7xxx_28nm_get_tunable() argument
480 return bcm_phy_downshift_get(phydev, (u8 *)data); in bcm7xxx_28nm_get_tunable()
486 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev, in bcm7xxx_28nm_set_tunable() argument
495 ret = bcm_phy_downshift_set(phydev, count); in bcm7xxx_28nm_set_tunable()
508 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_set_tunable()
512 return genphy_restart_aneg(phydev); in bcm7xxx_28nm_set_tunable()
515 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev, in bcm7xxx_28nm_get_phy_stats() argument
518 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_get_phy_stats()
520 bcm_phy_get_stats(phydev, priv->stats, stats, data); in bcm7xxx_28nm_get_phy_stats()
523 static int bcm7xxx_28nm_probe(struct phy_device *phydev) in bcm7xxx_28nm_probe() argument
528 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in bcm7xxx_28nm_probe()
532 phydev->priv = priv; in bcm7xxx_28nm_probe()
534 priv->stats = devm_kcalloc(&phydev->mdio.dev, in bcm7xxx_28nm_probe()
535 bcm_phy_get_sset_count(phydev), sizeof(u64), in bcm7xxx_28nm_probe()
540 priv->clk = devm_clk_get_optional(&phydev->mdio.dev, NULL); in bcm7xxx_28nm_probe()
554 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_probe()
559 static void bcm7xxx_28nm_remove(struct phy_device *phydev) in bcm7xxx_28nm_remove() argument
561 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_remove()