Lines Matching +full:0 +full:x1032
69 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
74 #define PI_PHY_K_S 0 /* Index to S phy */
75 #define PI_PHY_K_A 0 /* Index to A phy */
94 #define PI_FMC_DESCR_V_LEN 0
96 #define PI_FMC_DESCR_M_SOP 0x80000000
97 #define PI_FMC_DESCR_M_EOP 0x40000000
98 #define PI_FMC_DESCR_M_FSC 0x38000000
99 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
100 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
101 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
102 #define PI_FMC_DESCR_M_FSB 0x07C00000
103 #define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000
104 #define PI_FMC_DESCR_M_RCC_CRC 0x00100000
105 #define PI_FMC_DESCR_M_RCC_RRR 0x000E0000
106 #define PI_FMC_DESCR_M_RCC_DD 0x00018000
107 #define PI_FMC_DESCR_M_RCC_SS 0x00006000
108 #define PI_FMC_DESCR_M_RCC 0x003FE000
109 #define PI_FMC_DESCR_M_LEN 0x00001FFF
111 #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA
113 #define PI_FMC_DESCR_K_RRR_SUCCESS 0x00
114 #define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01
115 #define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02
116 #define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03
117 #define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04
118 #define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05
119 #define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06
120 #define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07
122 #define PI_FMC_DESCR_K_DD_NO_MATCH 0x0
123 #define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1
124 #define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2
125 #define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3
127 #define PI_FMC_DESCR_K_SS_NO_MATCH 0x0
128 #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1
129 #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2
130 #define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3
143 #define PI_STATE_K_RESET 0
155 #define PI_CMD_K_START 0x00
156 #define PI_CMD_K_FILTERS_SET 0x01
157 #define PI_CMD_K_FILTERS_GET 0x02
158 #define PI_CMD_K_CHARS_SET 0x03
159 #define PI_CMD_K_STATUS_CHARS_GET 0x04
160 #define PI_CMD_K_CNTRS_GET 0x05
161 #define PI_CMD_K_CNTRS_SET 0x06
162 #define PI_CMD_K_ADDR_FILTER_SET 0x07
163 #define PI_CMD_K_ADDR_FILTER_GET 0x08
164 #define PI_CMD_K_ERROR_LOG_CLEAR 0x09
165 #define PI_CMD_K_ERROR_LOG_GET 0x0A
166 #define PI_CMD_K_FDDI_MIB_GET 0x0B
167 #define PI_CMD_K_DEC_EXT_MIB_GET 0x0C
168 #define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D
169 #define PI_CMD_K_SNMP_SET 0x0E
170 #define PI_CMD_K_UNSOL_TEST 0x0F
171 #define PI_CMD_K_SMT_MIB_GET 0x10
172 #define PI_CMD_K_SMT_MIB_SET 0x11
173 #define PI_CMD_K_MAX 0x11 /* Must match last */
177 #define PI_ITEM_K_EOL 0x00 /* End-of-Item list */
178 #define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */
179 #define PI_ITEM_K_TVX 0x02 /* DECnet TVX */
180 #define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */
181 #define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */
182 #define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */
183 #define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */
184 #define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */
185 #define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */
186 #define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */
187 #define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */
188 #define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */
189 #define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */
190 #define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */
191 #define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */
192 #define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */
193 #define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */
194 #define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */
195 #define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */
196 #define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */
197 #define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */
198 #define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */
199 #define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */
200 #define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */
201 #define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */
202 #define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */
203 #define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */
204 #define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */
205 #define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */
206 #define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */
207 #define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */
208 #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */
209 #define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */
210 #define PI_ITEM_K_MAX 0x2C /* Must equal high item */
214 #define PI_K_FALSE 0 /* Generic false */
220 #define PI_FSTATE_K_BLOCK 0 /* Filter State */
225 #define PI_RSP_K_SUCCESS 0x00
226 #define PI_RSP_K_FAILURE 0x01
227 #define PI_RSP_K_WARNING 0x02
228 #define PI_RSP_K_LOOP_MODE_BAD 0x03
229 #define PI_RSP_K_ITEM_CODE_BAD 0x04
230 #define PI_RSP_K_TVX_BAD 0x05
231 #define PI_RSP_K_TREQ_BAD 0x06
232 #define PI_RSP_K_TOKEN_BAD 0x07
233 #define PI_RSP_K_NO_EOL 0x0C
234 #define PI_RSP_K_FILTER_STATE_BAD 0x0D
235 #define PI_RSP_K_CMD_TYPE_BAD 0x0E
236 #define PI_RSP_K_ADAPTER_STATE_BAD 0x0F
237 #define PI_RSP_K_RING_PURGER_BAD 0x10
238 #define PI_RSP_K_LEM_THRESHOLD_BAD 0x11
239 #define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12
240 #define PI_RSP_K_FLUSH_TIME_BAD 0x13
241 #define PI_RSP_K_NOT_IMPLEMENTED 0x14
242 #define PI_RSP_K_CONFIG_POLICY_BAD 0x15
243 #define PI_RSP_K_STATION_ACTION_BAD 0x16
244 #define PI_RSP_K_MAC_ACTION_BAD 0x17
245 #define PI_RSP_K_CON_POLICIES_BAD 0x18
246 #define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19
247 #define PI_RSP_K_TB_MAX_BAD 0x1A
248 #define PI_RSP_K_LER_CUTOFF_BAD 0x1B
249 #define PI_RSP_K_LER_ALARM_BAD 0x1C
250 #define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D
251 #define PI_RSP_K_MAC_T_REQ_BAD 0x1E
252 #define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F
253 #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20
254 #define PI_RSP_K_NO_SUCH_ENTRY 0x21
255 #define PI_RSP_K_T_NOTIFY_BAD 0x22
256 #define PI_RSP_K_TR_MAX_EXP_BAD 0x23
257 #define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24
258 #define PI_RSP_K_MAX_T_REQ_BAD 0x25
259 #define PI_RSP_K_FDX_ENB_DIS_BAD 0x26
260 #define PI_RSP_K_ITEM_INDEX_BAD 0x27
261 #define PI_RSP_K_PORT_ACTION_BAD 0x28
512 #define PI_GRP_K_SMT_STATION_ID 0x100A
513 #define PI_ITEM_K_SMT_STATION_ID 0x100B
514 #define PI_ITEM_K_SMT_OP_VERS_ID 0x100D
515 #define PI_ITEM_K_SMT_HI_VERS_ID 0x100E
516 #define PI_ITEM_K_SMT_LO_VERS_ID 0x100F
517 #define PI_ITEM_K_SMT_USER_DATA 0x1011
518 #define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012
520 #define PI_GRP_K_SMT_STATION_CONFIG 0x1014
521 #define PI_ITEM_K_SMT_MAC_CT 0x1015
522 #define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016
523 #define PI_ITEM_K_SMT_MASTER_CT 0x1017
524 #define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018
525 #define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019
526 #define PI_ITEM_K_SMT_CONFIG_POL 0x101A
527 #define PI_ITEM_K_SMT_CONN_POL 0x101B
528 #define PI_ITEM_K_SMT_T_NOTIFY 0x101D
529 #define PI_ITEM_K_SMT_STAT_POL 0x101E
530 #define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F
531 #define PI_ITEM_K_SMT_PORT_INDEXES 0x1020
532 #define PI_ITEM_K_SMT_MAC_INDEXES 0x1021
533 #define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022
535 #define PI_GRP_K_SMT_STATUS 0x1028
536 #define PI_ITEM_K_SMT_ECM_STATE 0x1029
537 #define PI_ITEM_K_SMT_CF_STATE 0x102A
538 #define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C
539 #define PI_ITEM_K_SMT_STATION_STATUS 0x102D
540 #define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E
542 #define PI_GRP_K_SMT_MIB_OPERATION 0x1032
543 #define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033
544 #define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034
546 #define PI_ITEM_K_SMT_STATION_ACT 0x103C
548 #define PI_GRP_K_MAC_CAPABILITIES 0x200A
549 #define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B
550 #define PI_ITEM_K_MAC_T_MAX_CAP 0x200D
551 #define PI_ITEM_K_MAC_TVX_CAP 0x200E
553 #define PI_GRP_K_MAC_CONFIG 0x2014
554 #define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016
555 #define PI_ITEM_K_MAC_CURRENT_PATH 0x2017
556 #define PI_ITEM_K_MAC_UP_NBR 0x2018
557 #define PI_ITEM_K_MAC_DOWN_NBR 0x2019
558 #define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A
559 #define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B
560 #define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D
561 #define PI_ITEM_K_MAC_REQ_PATHS 0x2020
562 #define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021
563 #define PI_ITEM_K_MAC_INDEX 0x2022
565 #define PI_GRP_K_MAC_ADDRESS 0x2028
566 #define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029
568 #define PI_GRP_K_MAC_OPERATION 0x2032
569 #define PI_ITEM_K_MAC_TREQ 0x2033
570 #define PI_ITEM_K_MAC_TNEG 0x2034
571 #define PI_ITEM_K_MAC_TMAX 0x2035
572 #define PI_ITEM_K_MAC_TVX_VALUE 0x2036
574 #define PI_GRP_K_MAC_COUNTERS 0x2046
575 #define PI_ITEM_K_MAC_FRAME_CT 0x2047
576 #define PI_ITEM_K_MAC_COPIED_CT 0x2048
577 #define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049
578 #define PI_ITEM_K_MAC_ERROR_CT 0x2051
579 #define PI_ITEM_K_MAC_LOST_CT 0x2052
581 #define PI_GRP_K_MAC_FRM_ERR_COND 0x205A
582 #define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F
583 #define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060
585 #define PI_GRP_K_MAC_STATUS 0x206E
586 #define PI_ITEM_K_MAC_RMT_STATE 0x206F
587 #define PI_ITEM_K_MAC_DA_FLAG 0x2070
588 #define PI_ITEM_K_MAC_UNDA_FLAG 0x2071
589 #define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072
590 #define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074
591 #define PI_ITEM_K_MAC_HW_PRESENT 0x2075
592 #define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076
594 #define PI_GRP_K_PATH_CONFIG 0x320A
595 #define PI_ITEM_K_PATH_INDEX 0x320B
596 #define PI_ITEM_K_PATH_CONFIGURATION 0x3212
597 #define PI_ITEM_K_PATH_TVX_LB 0x3215
598 #define PI_ITEM_K_PATH_T_MAX_LB 0x3216
599 #define PI_ITEM_K_PATH_MAX_T_REQ 0x3217
601 #define PI_GRP_K_PORT_CONFIG 0x400A
602 #define PI_ITEM_K_PORT_MY_TYPE 0x400C
603 #define PI_ITEM_K_PORT_NBR_TYPE 0x400D
604 #define PI_ITEM_K_PORT_CONN_POLS 0x400E
605 #define PI_ITEM_K_PORT_MAC_INDICATED 0x400F
606 #define PI_ITEM_K_PORT_CURRENT_PATH 0x4010
607 #define PI_ITEM_K_PORT_REQ_PATHS 0x4011
608 #define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012
609 #define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013
610 #define PI_ITEM_K_PORT_PMD_CLASS 0x4016
611 #define PI_ITEM_K_PORT_CONN_CAPS 0x4017
612 #define PI_ITEM_K_PORT_INDEX 0x401D
614 #define PI_GRP_K_PORT_OPERATION 0x401E
615 #define PI_ITEM_K_PORT_BS_FLAG 0x4021
617 #define PI_GRP_K_PORT_ERR_CNTRS 0x4028
618 #define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A
620 #define PI_GRP_K_PORT_LER 0x4032
621 #define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033
622 #define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034
623 #define PI_ITEM_K_PORT_LEM_CT 0x4035
624 #define PI_ITEM_K_PORT_LER_CUTOFF 0x403A
625 #define PI_ITEM_K_PORT_LER_ALARM 0x403B
627 #define PI_GRP_K_PORT_STATUS 0x403C
628 #define PI_ITEM_K_PORT_CONNECT_STATE 0x403D
629 #define PI_ITEM_K_PORT_PCM_STATE 0x403E
630 #define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F
631 #define PI_ITEM_K_PORT_LER_FLAG 0x4040
632 #define PI_ITEM_K_PORT_HW_PRESENT 0x4041
634 #define PI_ITEM_K_PORT_ACT 0x4046
956 #define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */
995 #define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */
997 #define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */
1079 #define PI_CONS_M_RCV_INDEX 0x000000FF
1080 #define PI_CONS_M_XMT_INDEX 0x00FF0000
1081 #define PI_CONS_V_RCV_INDEX 0
1086 #define PI_CONS_BLK_K_XMT_RCV 0x00
1087 #define PI_CONS_BLK_K_SMT_HOST 0x08
1088 #define PI_CONS_BLK_K_UNSOL 0x10
1089 #define PI_CONS_BLK_K_CMD_RSP 0x18
1090 #define PI_CONS_BLK_K_CMD_REQ 0x20
1094 #define PI_DESCR_BLK_K_RCV_DATA 0x0000
1095 #define PI_DESCR_BLK_K_XMT_DATA 0x0800
1096 #define PI_DESCR_BLK_K_SMT_HOST 0x1000
1097 #define PI_DESCR_BLK_K_UNSOL 0x1200
1098 #define PI_DESCR_BLK_K_CMD_RSP 0x1280
1099 #define PI_DESCR_BLK_K_CMD_REQ 0x1300
1114 #define PI_RCV_DESCR_M_SOP 0x80000000
1115 #define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000
1116 #define PI_RCV_DESCR_M_MBZ 0x60000000
1117 #define PI_RCV_DESCR_M_SEG_LEN 0x1F800000
1118 #define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000
1119 #define PI_RCV_DESCR_M_SEG_CNT 0x000F0000
1120 #define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF
1128 #define PI_RCV_DESCR_V_BUFF_HI 0
1138 #define PI_XMT_DESCR_M_SOP 0x80000000
1139 #define PI_XMT_DESCR_M_EOP 0x40000000
1140 #define PI_XMT_DESCR_M_MBZ 0x20000000
1141 #define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000
1142 #define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF
1148 #define PI_XMT_DESCR_V_BUFF_HI 0
1171 #define PI_PDQ_K_REG_PORT_RESET 0x00000000
1172 #define PI_PDQ_K_REG_HOST_DATA 0x00000004
1173 #define PI_PDQ_K_REG_PORT_CTRL 0x00000008
1174 #define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C
1175 #define PI_PDQ_K_REG_PORT_DATA_B 0x00000010
1176 #define PI_PDQ_K_REG_PORT_STATUS 0x00000014
1177 #define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018
1178 #define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C
1179 #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020
1180 #define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024
1181 #define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028
1182 #define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C
1183 #define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030
1184 #define PI_PDQ_K_REG_UNSOL_PROD 0x00000034
1188 #define PI_PCTRL_M_CMD_ERROR 0x8000
1189 #define PI_PCTRL_M_BLAST_FLASH 0x4000
1190 #define PI_PCTRL_M_HALT 0x2000
1191 #define PI_PCTRL_M_COPY_DATA 0x1000
1192 #define PI_PCTRL_M_ERROR_LOG_START 0x0800
1193 #define PI_PCTRL_M_ERROR_LOG_READ 0x0400
1194 #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200
1195 #define PI_PCTRL_M_INIT 0x0100
1196 #define PI_PCTRL_M_INIT_START 0x0080
1197 #define PI_PCTRL_M_CONS_BLOCK 0x0040
1198 #define PI_PCTRL_M_UNINIT 0x0020
1199 #define PI_PCTRL_M_RING_MEMBER 0x0010
1200 #define PI_PCTRL_M_MLA 0x0008
1201 #define PI_PCTRL_M_FW_REV_READ 0x0004
1202 #define PI_PCTRL_M_DEV_SPECIFIC 0x0002
1203 #define PI_PCTRL_M_SUB_CMD 0x0001
1207 #define PI_SUB_CMD_K_LINK_UNINIT 0x0001
1208 #define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002
1209 #define PI_SUB_CMD_K_PDQ_REV_GET 0x0004
1210 #define PI_SUB_CMD_K_HW_REV_GET 0x0008
1214 #define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */
1222 #define PI_PDATA_A_RESET_M_UPGRADE 0x00000001
1223 #define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002
1224 #define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004
1228 #define PI_PDATA_A_MLA_K_LO 0
1233 #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000
1234 #define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC
1235 #define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002
1236 #define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001
1241 #define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0
1259 #define PI_PSTATUS_V_HALT_ID 0
1261 #define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000
1262 #define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000
1263 #define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000
1264 #define PI_PSTATUS_M_UNSOL_PENDING 0x10000000
1265 #define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000
1266 #define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000
1267 #define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000
1268 #define PI_PSTATUS_M_RESERVED_1 0x01FF0000
1269 #define PI_PSTATUS_M_RESERVED_2 0x0000F800
1270 #define PI_PSTATUS_M_STATE 0x00000700
1271 #define PI_PSTATUS_M_HALT_ID 0x000000FF
1276 #define PI_HALT_ID_K_SELFTEST_TIMEOUT 0
1288 #define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */
1289 #define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000
1290 #define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */
1291 #define PI_HOST_INT_M_UNSOL_ENB 0x20000000
1292 #define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000
1293 #define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000
1294 #define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000
1295 #define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */
1296 #define PI_HOST_INT_M_1MS 0x00000080
1297 #define PI_HOST_INT_M_20MS 0x00000040
1298 #define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020
1299 #define PI_HOST_INT_M_STATE_CHANGE 0x00000010
1300 #define PI_HOST_INT_M_XMT_FLUSH 0x00000008
1301 #define PI_HOST_INT_M_NXM 0x00000004
1302 #define PI_HOST_INT_M_PM_PAR_ERR 0x00000002
1303 #define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001
1312 #define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */
1320 #define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0
1322 #define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF
1323 #define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000
1324 #define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF
1325 #define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F
1327 /* Type 0 Interrupt Status Register */
1329 #define PI_TYPE_0_STAT_M_1MS 0x00000080
1330 #define PI_TYPE_0_STAT_M_20MS 0x00000040
1331 #define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020
1332 #define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010
1333 #define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008
1334 #define PI_TYPE_0_STAT_M_NXM 0x00000004
1335 #define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002
1336 #define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001
1345 #define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0
1477 #define PI_TC_K_CSR_OFFSET 0x100000
1478 #define PI_TC_K_CSR_LEN 0x40 /* 64 bytes */
1482 #define PI_ESIC_K_CSR_IO_LEN 0x40 /* 64 bytes */
1483 #define PI_ESIC_K_BURST_HOLDOFF_LEN 0x04 /* 4 bytes */
1484 #define PI_ESIC_K_ESIC_CSR_LEN 0x40 /* 64 bytes */
1486 #define PI_DEFEA_K_CSR_IO 0x000
1487 #define PI_DEFEA_K_BURST_HOLDOFF 0x040
1488 #define PI_ESIC_K_ESIC_CSR 0xC80
1490 #define PI_ESIC_K_SLOT_ID 0xC80
1491 #define PI_ESIC_K_SLOT_CNTRL 0xC84
1492 #define PI_ESIC_K_MEM_ADD_CMP_0 0xC85
1493 #define PI_ESIC_K_MEM_ADD_CMP_1 0xC86
1494 #define PI_ESIC_K_MEM_ADD_CMP_2 0xC87
1495 #define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88
1496 #define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89
1497 #define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A
1498 #define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B
1499 #define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C
1500 #define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D
1501 #define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E
1502 #define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F
1503 #define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90
1504 #define PI_ESIC_K_IO_ADD_CMP_0_0 0xC91
1505 #define PI_ESIC_K_IO_ADD_CMP_0_1 0xC92
1506 #define PI_ESIC_K_IO_ADD_CMP_1_0 0xC93
1507 #define PI_ESIC_K_IO_ADD_CMP_1_1 0xC94
1508 #define PI_ESIC_K_IO_ADD_CMP_2_0 0xC95
1509 #define PI_ESIC_K_IO_ADD_CMP_2_1 0xC96
1510 #define PI_ESIC_K_IO_ADD_CMP_3_0 0xC97
1511 #define PI_ESIC_K_IO_ADD_CMP_3_1 0xC98
1512 #define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99
1513 #define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A
1514 #define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B
1515 #define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C
1516 #define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D
1517 #define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E
1518 #define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F
1519 #define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0
1520 #define PI_ESIC_K_MOD_CONFIG_1 0xCA1
1521 #define PI_ESIC_K_MOD_CONFIG_2 0xCA2
1522 #define PI_ESIC_K_MOD_CONFIG_3 0xCA3
1523 #define PI_ESIC_K_MOD_CONFIG_4 0xCA4
1524 #define PI_ESIC_K_MOD_CONFIG_5 0xCA5
1525 #define PI_ESIC_K_MOD_CONFIG_6 0xCA6
1526 #define PI_ESIC_K_MOD_CONFIG_7 0xCA7
1527 #define PI_ESIC_K_DIP_SWITCH 0xCA8
1528 #define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9
1529 #define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA
1530 #define PI_ESIC_K_DMA_CONFIG 0xCAB
1531 #define PI_ESIC_K_INPUT_PORT 0xCAC
1532 #define PI_ESIC_K_OUTPUT_PORT 0xCAD
1533 #define PI_ESIC_K_FUNCTION_CNTRL 0xCAE
1537 #define PI_FUNCTION_CNTRL_M_IOCS0 0x01
1538 #define PI_FUNCTION_CNTRL_M_IOCS1 0x02
1539 #define PI_FUNCTION_CNTRL_M_IOCS2 0x04
1540 #define PI_FUNCTION_CNTRL_M_IOCS3 0x08
1541 #define PI_FUNCTION_CNTRL_M_MEMCS0 0x10
1542 #define PI_FUNCTION_CNTRL_M_MEMCS1 0x20
1543 #define PI_FUNCTION_CNTRL_M_DMA 0x80
1547 #define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */
1548 #define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */
1549 #define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */
1553 #define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC
1554 #define PI_BURST_HOLDOFF_M_RESERVED 0x02
1555 #define PI_BURST_HOLDOFF_M_MEM_MAP 0x01
1559 #define PI_BURST_HOLDOFF_V_MEM_MAP 0
1563 #define PI_MEM_ADD_MASK_M 0x3ff
1567 #define PI_IO_CMP_M_SLOT 0xf0
1573 #define PI_CONFIG_STAT_0_M_PEND 0x80
1574 #define PI_CONFIG_STAT_0_M_RES_1 0x40
1575 #define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20
1576 #define PI_CONFIG_STAT_0_M_IREQ_IN 0x10
1577 #define PI_CONFIG_STAT_0_M_INT_ENB 0x08
1578 #define PI_CONFIG_STAT_0_M_RES_0 0x04
1579 #define PI_CONFIG_STAT_0_M_IRQ 0x03
1587 #define PI_CONFIG_STAT_0_V_IRQ 0
1589 #define PI_CONFIG_STAT_0_IRQ_K_9 0
1596 #define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */
1597 #define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */
1598 #define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */
1599 #define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */
1600 #define DEFEA_PROD_ID_4 0x0430A310 /* DEC product 300, rev 4 */
1603 /* Digital PFI Specification v1.0 Definitions */
1608 #define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */
1609 #define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */
1610 #define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */
1611 #define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */
1612 #define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */
1616 #define PFI_K_REG_RESERVED_0 0X00000038
1617 #define PFI_K_REG_RESERVED_1 0X0000003C
1618 #define PFI_K_REG_MODE_CTRL 0X00000040
1619 #define PFI_K_REG_STATUS 0X00000044
1620 #define PFI_K_REG_FIFO_WRITE 0X00000048
1621 #define PFI_K_REG_FIFO_READ 0X0000004C
1625 #define PFI_MODE_M_RESERVED 0XFFFFFFF0
1626 #define PFI_MODE_M_TGT_ABORT_ENB 0X00000008
1627 #define PFI_MODE_M_PDQ_INT_ENB 0X00000004
1628 #define PFI_MODE_M_PFI_INT_ENB 0X00000002
1629 #define PFI_MODE_M_DMA_ENB 0X00000001
1635 #define PFI_MODE_V_DMA_ENB 0
1637 #define PFI_MODE_K_ALL_DISABLE 0X00000000
1641 #define PFI_STATUS_M_RESERVED 0XFFFFFFC0
1642 #define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */
1643 #define PFI_STATUS_M_PDQ_INT 0X00000010
1644 #define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008
1645 #define PFI_STATUS_M_FIFO_FULL 0X00000004
1646 #define PFI_STATUS_M_FIFO_EMPTY 0X00000002
1647 #define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001
1655 #define PFI_STATUS_V_DMA_IN_PROGRESS 0
1657 #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */
1658 #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */
1659 #define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */
1660 #define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */
1664 #define DFX_K_SUCCESS 0 /* routine succeeded */
1677 #define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */
1686 #define XMT_BUFF_K_FC 0 /* one byte frame control */
1706 #define DFX_UNMASK_INTERRUPTS 0