ethernet/xilinx/xilinx_axienet.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
21 #define XAE_MTU			      1500 /* Max MTU of an Ethernet frame */
22 #define XAE_JUMBO_MTU		      9000 /* Max MTU of a jumbo Eth. frame */
109 #define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /* All control bits */
130 #define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /* All control bits */
140 #define XAXIDMA_BD_STS_ALL_MASK		0xFC000000 /* All status bits */
147 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
153 #define XAE_UAWL_OFFSET		0x00000020 /* Unicast address word lower */
154 #define XAE_UAWU_OFFSET		0x00000024 /* Unicast address word upper */
158 #define XAE_RCW0_OFFSET		0x00000400 /* Rx Configuration Word 0 */
159 #define XAE_RCW1_OFFSET		0x00000404 /* Rx Configuration Word 1 */
169 #define XAE_UAW0_OFFSET		0x00000700 /* Unicast address word 0 */
170 #define XAE_UAW1_OFFSET		0x00000704 /* Unicast address word 1 */
193 #define XAE_RAF_TXVTAGMODE_SHIFT	3 /* Tx Tag mode shift bits */
194 #define XAE_RAF_RXVTAGMODE_SHIFT	5 /* Rx Tag mode shift bits */
195 #define XAE_RAF_TXVSTRPMODE_SHIFT	7 /* Tx strip mode shift bits*/
196 #define XAE_RAF_RXVSTRPMODE_SHIFT	9 /* Rx Strip mode shift bits*/
200 /* Transmit inter-frame gap adjustment value */
219 /* INT bits that indicate receive errors */
223 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
227 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
234 /* In-Band FCS enable (FCS not stripped) */
242 /* Pause frame source address bits [47:32]. Bits [31:0] are
250 /* In-Band FCS enable (FCS not generated) */
254 /* Inter-frame gap adjustment enable */
276 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
305 /* Station address bits [47:32]; Station address
306  * bits [31:0] are stored in register UAW0
343  * struct axidma_bd - Axi Dma buffer descriptor layout
345  * @next_msb:     MM2S/S2MM Next Descriptor Pointer (high 32 bits)
347  * @phys_msb:     MM2S/S2MM Buffer Address (high 32 bits)
360 	u32 next_msb;	/* high 32 bits for IP >= v7.1, reserved on older IP */
376  * struct axienet_local - axienet private per device data
387  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
388  * @options:	AxiEthernet option word
440 	u32 options;			/* Current options word */
465  * struct axiethernet_option - Used to set axi ethernet hardware options
477  * axienet_ior - Memory mapped Axi Ethernet register read
487 	return ioread32(lp->regs + offset);  in axienet_ior()
496  * axienet_iow - Memory mapped Axi Ethernet register write
507 	iowrite32(value, lp->regs + offset);  in axienet_iow()