ethernet/xilinx/xilinx_axienet.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Definitions for Xilinx Axi Ethernet device driver.
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
72 /* Axi DMA Register definitions */
144 /* Axi Ethernet registers definition */
147 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
165 #define XAE_MDIO_MC_OFFSET	0x00000500 /* MII Management Config */
179 /* Bit Masks for Axi Ethernet RAF register */
198 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
200 /* Transmit inter-frame gap adjustment value */
203 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
223 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
227 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
231 /* Bit masks for Axi Ethernet RCW1 register */
234 /* In-Band FCS enable (FCS not stripped) */
247 /* Bit masks for Axi Ethernet TC register */
250 /* In-Band FCS enable (FCS not generated) */
254 /* Inter-frame gap adjustment enable */
257 /* Bit masks for Axi Ethernet FCC register */
261 /* Bit masks for Axi Ethernet EMMC register */
273 /* Bit masks for Axi Ethernet PHYC register */
276 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
285 /* Bit masks for Axi Ethernet MDIO interface MC register */
289 /* Bit masks for Axi Ethernet MDIO interface MCR register */
301 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
304 /* Bit masks for Axi Ethernet UAW1 register */
310 /* Bit masks for Axi Ethernet FMI register */
316 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
327 /* Axi Ethernet Synthesis features */
343  * struct axidma_bd - Axi Dma buffer descriptor layout
376  * struct axienet_local - axienet private per device data
384  * @dma_err_tasklet: Tasklet structure to process Axi DMA errors
387  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
422 	/* Clock for AXI bus */
465  * struct axiethernet_option - Used to set axi ethernet hardware options
477  * axienet_ior - Memory mapped Axi Ethernet register read
479  * @offset:     Address offset from the base address of Axi Ethernet core
481  * Return: The contents of the Axi Ethernet register
487 	return ioread32(lp->regs + offset);  in axienet_ior()
496  * axienet_iow - Memory mapped Axi Ethernet register write
498  * @offset:     Address offset from the base address of Axi Ethernet core
499  * @value:      Value to be written into the Axi Ethernet register
501  * This function writes the desired value into the corresponding Axi Ethernet
507 	iowrite32(value, lp->regs + offset);  in axienet_iow()