70 /* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
72 						 (0x13c + (4 * (x - 2))))
76 #define QSGMII_PHY_TX_DRIVER_EN			BIT(3)
95 	struct device *dev = &gmac->pdev->dev;  in get_clk_div_sgmii()
113 		return -EINVAL;  in get_clk_div_sgmii()
121 	struct device *dev = &gmac->pdev->dev;  in get_clk_div_rgmii()
139 		return -EINVAL;  in get_clk_div_rgmii()
150 	switch (gmac->phy_mode) {  in ipq806x_gmac_set_speed()
153 		clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |  in ipq806x_gmac_set_speed()
154 			   NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);  in ipq806x_gmac_set_speed()
159 		clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |  in ipq806x_gmac_set_speed()
160 			   NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);  in ipq806x_gmac_set_speed()
164 		dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",  in ipq806x_gmac_set_speed()
165 			phy_modes(gmac->phy_mode));  in ipq806x_gmac_set_speed()
166 		return -EINVAL;  in ipq806x_gmac_set_speed()
170 	regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);  in ipq806x_gmac_set_speed()
172 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);  in ipq806x_gmac_set_speed()
175 	regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);  in ipq806x_gmac_set_speed()
177 		 << NSS_COMMON_CLK_DIV_OFFSET(gmac->id));  in ipq806x_gmac_set_speed()
178 	val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);  in ipq806x_gmac_set_speed()
179 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);  in ipq806x_gmac_set_speed()
182 	regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);  in ipq806x_gmac_set_speed()
184 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);  in ipq806x_gmac_set_speed()
191 	struct device *dev = &gmac->pdev->dev;  in ipq806x_gmac_of_parse()
194 	ret = of_get_phy_mode(dev->of_node, &gmac->phy_mode);  in ipq806x_gmac_of_parse()
197 		return -EINVAL;  in ipq806x_gmac_of_parse()
200 	if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {  in ipq806x_gmac_of_parse()
202 		return -EINVAL;  in ipq806x_gmac_of_parse()
207 	 * them from 0 to 3 here.  in ipq806x_gmac_of_parse()
209 	if (gmac->id > 3) {  in ipq806x_gmac_of_parse()
211 		return -EINVAL;  in ipq806x_gmac_of_parse()
214 	gmac->core_clk = devm_clk_get(dev, "stmmaceth");  in ipq806x_gmac_of_parse()
215 	if (IS_ERR(gmac->core_clk)) {  in ipq806x_gmac_of_parse()
217 		return PTR_ERR(gmac->core_clk);  in ipq806x_gmac_of_parse()
219 	clk_set_rate(gmac->core_clk, 266000000);  in ipq806x_gmac_of_parse()
222 	gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,  in ipq806x_gmac_of_parse()
223 							   "qcom,nss-common");  in ipq806x_gmac_of_parse()
224 	if (IS_ERR(gmac->nss_common)) {  in ipq806x_gmac_of_parse()
225 		dev_err(dev, "missing nss-common node\n");  in ipq806x_gmac_of_parse()
226 		return PTR_ERR(gmac->nss_common);  in ipq806x_gmac_of_parse()
230 	gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,  in ipq806x_gmac_of_parse()
231 							   "qcom,qsgmii-csr");  in ipq806x_gmac_of_parse()
232 	if (IS_ERR(gmac->qsgmii_csr))  in ipq806x_gmac_of_parse()
233 		dev_err(dev, "missing qsgmii-csr node\n");  in ipq806x_gmac_of_parse()
235 	return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);  in ipq806x_gmac_of_parse()
249 	struct device *dev = &pdev->dev;  in ipq806x_gmac_probe()
264 		err = -ENOMEM;  in ipq806x_gmac_probe()
268 	gmac->pdev = pdev;  in ipq806x_gmac_probe()
276 	regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,  in ipq806x_gmac_probe()
284 	switch (gmac->phy_mode) {  in ipq806x_gmac_probe()
292 		dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",  in ipq806x_gmac_probe()
293 			phy_modes(gmac->phy_mode));  in ipq806x_gmac_probe()
294 		err = -EINVAL;  in ipq806x_gmac_probe()
297 	regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);  in ipq806x_gmac_probe()
300 	regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);  in ipq806x_gmac_probe()
301 	val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));  in ipq806x_gmac_probe()
302 	switch (gmac->phy_mode) {  in ipq806x_gmac_probe()
304 		val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<  in ipq806x_gmac_probe()
305 			NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);  in ipq806x_gmac_probe()
308 		val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<  in ipq806x_gmac_probe()
309 			NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);  in ipq806x_gmac_probe()
312 		dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",  in ipq806x_gmac_probe()
313 			phy_modes(gmac->phy_mode));  in ipq806x_gmac_probe()
314 		err = -EINVAL;  in ipq806x_gmac_probe()
317 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);  in ipq806x_gmac_probe()
320 	regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);  in ipq806x_gmac_probe()
321 	val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);  in ipq806x_gmac_probe()
322 	switch (gmac->phy_mode) {  in ipq806x_gmac_probe()
324 		val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |  in ipq806x_gmac_probe()
325 			NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);  in ipq806x_gmac_probe()
328 		val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |  in ipq806x_gmac_probe()
329 				NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);  in ipq806x_gmac_probe()
335 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);  in ipq806x_gmac_probe()
337 	if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {  in ipq806x_gmac_probe()
338 		regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),  in ipq806x_gmac_probe()
351 	plat_dat->has_gmac = true;  in ipq806x_gmac_probe()
352 	plat_dat->bsp_priv = gmac;  in ipq806x_gmac_probe()
353 	plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;  in ipq806x_gmac_probe()
354 	plat_dat->multicast_filter_bins = 0;  in ipq806x_gmac_probe()
356 	err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);  in ipq806x_gmac_probe()
369 	{ .compatible = "qcom,ipq806x-gmac" },
378 		.name		= "ipq806x-gmac-dwmac",
386 MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");