Lines Matching +full:axi +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
41 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
46 return -ENODEV; in stmmac_pci_find_phy_addr()
48 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
49 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
52 if (func_data->func == func) in stmmac_pci_find_phy_addr()
53 return func_data->phy_addr; in stmmac_pci_find_phy_addr()
55 return -ENODEV; in stmmac_pci_find_phy_addr()
65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); in serdes_status_poll()
69 } while (--retries); in serdes_status_poll()
71 return -ETIMEDOUT; in serdes_status_poll()
81 if (!intel_priv->mdio_adhoc_addr) in intel_serdes_powerup()
84 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_serdes_powerup()
87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
98 dev_err(priv->device, "Serdes PLL clk request timeout\n"); in intel_serdes_powerup()
103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
114 dev_err(priv->device, "Serdes assert lane reset timeout\n"); in intel_serdes_powerup()
119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
133 dev_err(priv->device, "Serdes power state P0 timeout.\n"); in intel_serdes_powerup()
147 if (!intel_priv->mdio_adhoc_addr) in intel_serdes_powerdown()
150 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_serdes_powerdown()
153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
167 dev_err(priv->device, "Serdes power state P3 timeout\n"); in intel_serdes_powerdown()
171 /* de-assert clk_req */ in intel_serdes_powerdown()
172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
176 /* check for clk_ack de-assert */ in intel_serdes_powerdown()
183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); in intel_serdes_powerdown()
187 /* de-assert lane reset */ in intel_serdes_powerdown()
188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
192 /* check for de-assert lane reset reflection */ in intel_serdes_powerdown()
199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); in intel_serdes_powerdown()
206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
207 plat->has_gmac = 1; in common_default_data()
208 plat->force_sf_dma_mode = 1; in common_default_data()
210 plat->mdio_bus_data->needs_reset = true; in common_default_data()
213 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
216 plat->unicast_filter_entries = 1; in common_default_data()
219 plat->maxmtu = JUMBO_LEN; in common_default_data()
222 plat->tx_queues_to_use = 1; in common_default_data()
223 plat->rx_queues_to_use = 1; in common_default_data()
225 /* Disable Priority config by default */ in common_default_data()
226 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
227 plat->rx_queues_cfg[0].use_prio = false; in common_default_data()
230 plat->rx_queues_cfg[0].pkt_route = 0x0; in common_default_data()
239 plat->clk_csr = 5; in intel_mgbe_common_data()
240 plat->has_gmac = 0; in intel_mgbe_common_data()
241 plat->has_gmac4 = 1; in intel_mgbe_common_data()
242 plat->force_sf_dma_mode = 0; in intel_mgbe_common_data()
243 plat->tso_en = 1; in intel_mgbe_common_data()
245 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; in intel_mgbe_common_data()
247 for (i = 0; i < plat->rx_queues_to_use; i++) { in intel_mgbe_common_data()
248 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
249 plat->rx_queues_cfg[i].chan = i; in intel_mgbe_common_data()
251 /* Disable Priority config by default */ in intel_mgbe_common_data()
252 plat->rx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
255 plat->rx_queues_cfg[i].pkt_route = 0x0; in intel_mgbe_common_data()
258 for (i = 0; i < plat->tx_queues_to_use; i++) { in intel_mgbe_common_data()
259 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
261 /* Disable Priority config by default */ in intel_mgbe_common_data()
262 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
266 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; in intel_mgbe_common_data()
267 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; in intel_mgbe_common_data()
269 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; in intel_mgbe_common_data()
270 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
271 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
272 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
273 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
274 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
275 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
276 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
277 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()
279 plat->dma_cfg->pbl = 32; in intel_mgbe_common_data()
280 plat->dma_cfg->pblx8 = true; in intel_mgbe_common_data()
281 plat->dma_cfg->fixed_burst = 0; in intel_mgbe_common_data()
282 plat->dma_cfg->mixed_burst = 0; in intel_mgbe_common_data()
283 plat->dma_cfg->aal = 0; in intel_mgbe_common_data()
285 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), in intel_mgbe_common_data()
287 if (!plat->axi) in intel_mgbe_common_data()
288 return -ENOMEM; in intel_mgbe_common_data()
290 plat->axi->axi_lpi_en = 0; in intel_mgbe_common_data()
291 plat->axi->axi_xit_frm = 0; in intel_mgbe_common_data()
292 plat->axi->axi_wr_osr_lmt = 1; in intel_mgbe_common_data()
293 plat->axi->axi_rd_osr_lmt = 1; in intel_mgbe_common_data()
294 plat->axi->axi_blen[0] = 4; in intel_mgbe_common_data()
295 plat->axi->axi_blen[1] = 8; in intel_mgbe_common_data()
296 plat->axi->axi_blen[2] = 16; in intel_mgbe_common_data()
298 plat->ptp_max_adj = plat->clk_ptp_rate; in intel_mgbe_common_data()
299 plat->eee_usecs_rate = plat->clk_ptp_rate; in intel_mgbe_common_data()
302 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, in intel_mgbe_common_data()
303 "stmmac-clk", NULL, 0, in intel_mgbe_common_data()
304 plat->clk_ptp_rate); in intel_mgbe_common_data()
306 if (IS_ERR(plat->stmmac_clk)) { in intel_mgbe_common_data()
307 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); in intel_mgbe_common_data()
308 plat->stmmac_clk = NULL; in intel_mgbe_common_data()
311 ret = clk_prepare_enable(plat->stmmac_clk); in intel_mgbe_common_data()
313 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_mgbe_common_data()
318 plat->multicast_filter_bins = HASH_TABLE_SIZE; in intel_mgbe_common_data()
321 plat->unicast_filter_entries = 1; in intel_mgbe_common_data()
324 plat->maxmtu = JUMBO_LEN; in intel_mgbe_common_data()
326 plat->vlan_fail_q_en = true; in intel_mgbe_common_data()
329 plat->vlan_fail_q = plat->rx_queues_to_use - 1; in intel_mgbe_common_data()
337 plat->rx_queues_to_use = 8; in ehl_common_data()
338 plat->tx_queues_to_use = 8; in ehl_common_data()
339 plat->clk_ptp_rate = 200000000; in ehl_common_data()
347 plat->bus_id = 1; in ehl_sgmii_data()
348 plat->phy_addr = 0; in ehl_sgmii_data()
349 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_sgmii_data()
351 plat->serdes_powerup = intel_serdes_powerup; in ehl_sgmii_data()
352 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_sgmii_data()
364 plat->bus_id = 1; in ehl_rgmii_data()
365 plat->phy_addr = 0; in ehl_rgmii_data()
366 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; in ehl_rgmii_data()
378 plat->bus_id = 2; in ehl_pse0_common_data()
379 plat->phy_addr = 1; in ehl_pse0_common_data()
386 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse0_rgmii1g_data()
397 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse0_sgmii1g_data()
398 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse0_sgmii1g_data()
399 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse0_sgmii1g_data()
410 plat->bus_id = 3; in ehl_pse1_common_data()
411 plat->phy_addr = 1; in ehl_pse1_common_data()
418 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse1_rgmii1g_data()
429 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse1_sgmii1g_data()
430 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse1_sgmii1g_data()
431 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse1_sgmii1g_data()
442 plat->rx_queues_to_use = 6; in tgl_common_data()
443 plat->tx_queues_to_use = 4; in tgl_common_data()
444 plat->clk_ptp_rate = 200000000; in tgl_common_data()
452 plat->bus_id = 1; in tgl_sgmii_data()
453 plat->phy_addr = 0; in tgl_sgmii_data()
454 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_data()
455 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_data()
456 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_data()
506 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
514 "6ES7647-0AA00-0YA2"),
551 plat->bus_id = pci_dev_id(pdev); in quark_default_data()
552 plat->phy_addr = ret; in quark_default_data()
553 plat->phy_interface = PHY_INTERFACE_MODE_RMII; in quark_default_data()
555 plat->dma_cfg->pbl = 16; in quark_default_data()
556 plat->dma_cfg->pblx8 = true; in quark_default_data()
557 plat->dma_cfg->fixed_burst = 1; in quark_default_data()
558 /* AXI (TODO) */ in quark_default_data()
577 * to take "ownership" of the device or an error code(-ve no) otherwise.
582 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; in intel_eth_pci_probe()
588 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); in intel_eth_pci_probe()
590 return -ENOMEM; in intel_eth_pci_probe()
592 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); in intel_eth_pci_probe()
594 return -ENOMEM; in intel_eth_pci_probe()
596 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
597 sizeof(*plat->mdio_bus_data), in intel_eth_pci_probe()
599 if (!plat->mdio_bus_data) in intel_eth_pci_probe()
600 return -ENOMEM; in intel_eth_pci_probe()
602 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), in intel_eth_pci_probe()
604 if (!plat->dma_cfg) in intel_eth_pci_probe()
605 return -ENOMEM; in intel_eth_pci_probe()
610 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", in intel_eth_pci_probe()
621 plat->bsp_priv = intel_priv; in intel_eth_pci_probe()
622 intel_priv->mdio_adhoc_addr = 0x15; in intel_eth_pci_probe()
624 ret = info->setup(pdev, plat); in intel_eth_pci_probe()
637 if (plat->eee_usecs_rate > 0) { in intel_eth_pci_probe()
640 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; in intel_eth_pci_probe()
644 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); in intel_eth_pci_probe()
647 clk_disable_unprepare(plat->stmmac_clk); in intel_eth_pci_probe()
648 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_eth_pci_probe()
663 struct net_device *ndev = dev_get_drvdata(&pdev->dev); in intel_eth_pci_remove()
666 stmmac_dvr_remove(&pdev->dev); in intel_eth_pci_remove()
670 clk_unregister_fixed_rate(priv->plat->stmmac_clk); in intel_eth_pci_remove()
747 .name = "intel-eth-pci",