1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21  ---------------------------------------------------------------------------*/
29  * Any 16-bit access is performed with two 8-bit accesses if the hardware
30  * can't do it directly. Most registers are 16-bit so those are mandatory.
37 		SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT));	\
45 		__val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
55 #include <asm/mach-types.h>
60 #define SMC_CAN_USE_8BIT	1
61 #define SMC_CAN_USE_16BIT	1
62 #define SMC_CAN_USE_32BIT	1
63 #define SMC_NOWAIT		1
65 #define SMC_IO_SHIFT		(lp->io_shift)
77 #define SMC_outb(v, a, r)	writeb(v, (a) + (r))  argument
78 #define SMC_outw(lp, v, a, r)						\  argument
80 		unsigned int __v = v, __smc_r = r;			\
89 #define SMC_outl(v, a, r)	writel(v, (a) + (r))  argument
96 #define SMC_IRQ_FLAGS		(-1)	/* from resource */
103 		unsigned int v = val << 16;  in _SMC_outw_align4()  local
104 		v |= readl(ioaddr + (reg & ~2)) & 0xffff;  in _SMC_outw_align4()
105 		writel(v, ioaddr + (reg & ~2));  in _SMC_outw_align4()
111 #define __SMC_outw(lp, v, a, r)						\  argument
112 	_SMC_outw_align4((v), (a), (r),					\
114 			 (lp)->cfg.pxa_u16_align4)
120 #define SMC_CAN_USE_16BIT	1
123 #define SMC_inb(a, r)		inb((a) + (r) - 0xa0000000)
124 #define SMC_inw(a, r)		inw((a) + (r) - 0xa0000000)
125 #define SMC_inl(a, r)		inl((a) + (r) - 0xa0000000)
126 #define SMC_outb(v, a, r)	outb(v, (a) + (r) - 0xa0000000)  argument
127 #define SMC_outw(lp, v, a, r)	outw(v, (a) + (r) - 0xa0000000)  argument
128 #define SMC_outl(v, a, r)	outl(v, (a) + (r) - 0xa0000000)  argument
129 #define SMC_insl(a, r, p, l)	insl((a) + (r) - 0xa0000000, p, l)
130 #define SMC_outsl(a, r, p, l)	outsl((a) + (r) - 0xa0000000, p, l)
131 #define SMC_insw(a, r, p, l)	insw((a) + (r) - 0xa0000000, p, l)
132 #define SMC_outsw(a, r, p, l)	outsw((a) + (r) - 0xa0000000, p, l)
138 #define SMC_CAN_USE_8BIT        1
139 #define SMC_CAN_USE_16BIT       1
140 #define SMC_CAN_USE_32BIT       1
141 #define SMC_NOWAIT              1
146 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))  argument
147 #define SMC_outw(lp, v, a, r)   writew(v, (a) + (r))  argument
148 #define SMC_outl(v, a, r)       writel(v, (a) + (r))  argument
160 #define SMC_CAN_USE_16BIT	1
162 #define SMC_NOWAIT		1
167 	while (l-- > 0)  in mcf_insw()
174 	while (l-- > 0)  in mcf_outsw()
179 #define SMC_outw(lp, v, a, r)	writew(_swapw(v), (a) + (r))  argument
186 #define SMC_CAN_USE_8BIT	1
192 #define SMC_outb(v, a, r)	iowrite8(v, (a) + (r))  argument
202 #define SMC_CAN_USE_8BIT	1
203 #define SMC_CAN_USE_16BIT	1
204 #define SMC_CAN_USE_32BIT	1
205 #define SMC_NOWAIT		1
207 #define SMC_IO_SHIFT		(lp->io_shift)
212 #define SMC_outb(v, a, r)	iowrite8(v, (a) + (r))  argument
213 #define SMC_outw(lp, v, a, r)	iowrite16(v, (a) + (r))  argument
214 #define SMC_outl(v, a, r)	iowrite32(v, (a) + (r))  argument
275 	/* on some platforms a u16 write must be 4-bytes aligned */
281 #define SMC_8BIT(p)	((p)->cfg.flags & SMC91X_USE_8BIT)
282 #define SMC_16BIT(p)	((p)->cfg.flags & SMC91X_USE_16BIT)
283 #define SMC_32BIT(p)	((p)->cfg.flags & SMC91X_USE_32BIT)
288  * always happening in irq context so no need to worry about races.  TX is
292 #include <linux/dma-mapping.h>
297 	smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
307 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
308 	tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,  in smc_pxa_dma_inpump()
312 		dma_async_issue_pending(lp->dma_chan);  in smc_pxa_dma_inpump()
314 			status = dmaengine_tx_status(lp->dma_chan, cookie,  in smc_pxa_dma_inpump()
319 		dmaengine_terminate_all(lp->dma_chan);  in smc_pxa_dma_inpump()
321 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
331 	/* fallback if no DMA available */  in smc_pxa_dma_insl()
332 	if (!lp->dma_chan) {  in smc_pxa_dma_insl()
341 		len--;  in smc_pxa_dma_insl()
347 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
348 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
351 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insl()
353 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insl()
366 	smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
374 	/* fallback if no DMA available */  in smc_pxa_dma_insw()
375 	if (!lp->dma_chan) {  in smc_pxa_dma_insw()
384 		len--;  in smc_pxa_dma_insw()
390 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
391 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
394 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insw()
396 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insw()
490 #define TCR_ENABLE	0x0001	// When 1 we can transmit
492 #define TCR_FORCOL	0x0004	// When 1 will force a collision
493 #define TCR_PAD_EN	0x0080	// When 1 will pad tx frames < 64 bytes w/0
494 #define TCR_NOCRC	0x0100	// When 1 will not append CRC to tx frames
495 #define TCR_MON_CSN	0x0400	// When 1 tx monitors carrier
496 #define TCR_FDUPLX    	0x0800  // When 1 enables full duplex operation
497 #define TCR_STP_SQET	0x1000	// When 1 stops tx if Signal Quality Error
498 #define TCR_EPH_LOOP	0x2000	// When 1 enables EPH block loopback
499 #define TCR_SWFDUP	0x8000	// When 1 enables Switched Full Duplex mode
555 #define RPC_SPEED	0x2000	// When 1 PHY is in 100Mbps mode.
556 #define RPC_DPLX	0x1000	// When 1 PHY is in Full-Duplex Mode
557 #define RPC_ANEG	0x0800	// When 1 PHY is in Auto-Negotiate Mode
579 /* BANK 1 */
580 #define CONFIG_REG(lp)	SMC_REG(lp, 0x0000,	1)
581 #define CONFIG_EXT_PHY	0x0200	// 1=external MII, 0=internal Phy
583 #define CONFIG_NO_WAIT	0x1000	// When 1 no extra wait states on ISA bus
586 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
591 /* BANK 1 */
592 #define BASE_REG(lp)	SMC_REG(lp, 0x0002, 1)
596 /* BANK 1 */
597 #define ADDR0_REG(lp)	SMC_REG(lp, 0x0004, 1)
598 #define ADDR1_REG(lp)	SMC_REG(lp, 0x0006, 1)
599 #define ADDR2_REG(lp)	SMC_REG(lp, 0x0008, 1)
603 /* BANK 1 */
604 #define GP_REG(lp)		SMC_REG(lp, 0x000A, 1)
608 /* BANK 1 */
609 #define CTL_REG(lp)		SMC_REG(lp, 0x000C, 1)
610 #define CTL_RCV_BAD	0x4000 // When 1 bad CRC packets are received
611 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
612 #define CTL_LE_ENABLE	0x0080 // When 1 enables Link Error interrupt
613 #define CTL_CR_ENABLE	0x0040 // When 1 enables Counter Rollover interrupt
614 #define CTL_TE_ENABLE	0x0020 // When 1 enables Transmit Error interrupt
623 #define MC_BUSY		1	// When 1 the last release has not completed
624 #define MC_NOP		(0<<5)	// No Op
625 #define MC_ALLOC	(1<<5) 	// OR with number of 256 byte packets
660 #define PTR_RCV		0x8000 // 1=Receive area, 0=Transmit area
662 #define PTR_READ	0x2000 // When 1 the operation is a read
716 #define ERCV_RCV_DISCRD	0x0080 // When 1 discards a packet being received
730 #define CHIP_91100FD	8
740 	/* 8 */ "SMC91C100FD",
771  * These phy registers are specific to our on-board phy.
774 // PHY Configuration Register 1
776 #define PHY_CFG1_LNKDIS		0x8000	// 1=Rx Link Detect Function disabled
777 #define PHY_CFG1_XMTDIS		0x4000	// 1=TP Transmitter Disabled
778 #define PHY_CFG1_XMTPDN		0x2000	// 1=TP Transmitter Powered Down
779 #define PHY_CFG1_BYPSCR		0x0400	// 1=Bypass scrambler/descrambler
780 #define PHY_CFG1_UNSCDS		0x0200	// 1=Unscramble Idle Reception Disable
781 #define PHY_CFG1_EQLZR		0x0100	// 1=Rx Equalizer Disabled
782 #define PHY_CFG1_CABLE		0x0080	// 1=STP(150ohm), 0=UTP(100ohm)
783 #define PHY_CFG1_RLVL0		0x0040	// 1=Rx Squelch level reduced by 4.5db
791 #define PHY_CFG2_APOLDIS	0x0020	// 1=Auto Polarity Correction disabled
792 #define PHY_CFG2_JABDIS		0x0010	// 1=Jabber disabled
793 #define PHY_CFG2_MREG		0x0008	// 1=Multiple register access (MII mgt)
794 #define PHY_CFG2_INTMDIO	0x0004	// 1=Interrupt signaled with MDIO pulseo
798 #define PHY_INT_INT		0x8000	// 1=bits have changed since last read
799 #define PHY_INT_LNKFAIL		0x4000	// 1=Link Not detected
800 #define PHY_INT_LOSSSYNC	0x2000	// 1=Descrambler has lost sync
801 #define PHY_INT_CWRD		0x1000	// 1=Invalid 4B5B code detected on rx
802 #define PHY_INT_SSD		0x0800	// 1=No Start Of Stream detected on rx
803 #define PHY_INT_ESD		0x0400	// 1=No End Of Stream detected on rx
804 #define PHY_INT_RPOL		0x0200	// 1=Reverse Polarity detected
805 #define PHY_INT_JAB		0x0100	// 1=Jabber detected
806 #define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
807 #define PHY_INT_DPLXDET		0x0040	// 1=Device in Full Duplex
835  * Note: the following macros do *not* select the bank -- this must
861  * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
865  * effects and use a 32-bit access.
867  * Enforce it on any 32-bit capable setup for now.
887 				: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
895 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
917 				: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
924 			SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp));	\
958 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));	\
998 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));	\
1012 		addr[0] = __v; addr[1] = __v >> 8;			\
1014 		addr[2] = __v; addr[3] = __v >> 8;			\
1016 		addr[4] = __v; addr[5] = __v >> 8;			\
1022 		SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1023 		SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1024 		SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1030 		SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1031 		SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1032 		SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1033 		SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1066 				__len -= 2;				\
1067 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1070 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1071 				__ioaddr = lp->datacs;			\
1075 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1078 			SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1095 				 * Back both source (on-chip) and	\
1103 				__ptr -= 2;				\
1108 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1109 				__ioaddr = lp->datacs;			\
1113 			SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\