Lines Matching +full:0 +full:x1100000
15 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
19 #define CRB_BLK(off) ((off >> 20) & 0x3f)
20 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21 #define CRB_WINDOW_2M (0x130060)
22 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23 #define CRB_INDIRECT_2M (0x1e0000UL)
52 {{{0, 0, 0, 0} } }, /* 0: PCI */
53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
54 {1, 0x0110000, 0x0120000, 0x130000},
55 {1, 0x0120000, 0x0122000, 0x124000},
56 {1, 0x0130000, 0x0132000, 0x126000},
57 {1, 0x0140000, 0x0142000, 0x128000},
58 {1, 0x0150000, 0x0152000, 0x12a000},
59 {1, 0x0160000, 0x0170000, 0x110000},
60 {1, 0x0170000, 0x0172000, 0x12e000},
61 {0, 0x0000000, 0x0000000, 0x000000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {1, 0x01e0000, 0x01e0800, 0x122000},
68 {0, 0x0000000, 0x0000000, 0x000000} } },
69 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
70 {{{0, 0, 0, 0} } }, /* 3: */
71 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
72 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
73 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
74 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
75 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
76 {0, 0x0000000, 0x0000000, 0x000000},
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {1, 0x08f0000, 0x08f2000, 0x172000} } },
91 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x09f0000, 0x09f2000, 0x176000} } },
107 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
123 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
139 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
140 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
141 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
142 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
143 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
144 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
145 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
146 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
147 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
148 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
149 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
150 {{{0, 0, 0, 0} } }, /* 23: */
151 {{{0, 0, 0, 0} } }, /* 24: */
152 {{{0, 0, 0, 0} } }, /* 25: */
153 {{{0, 0, 0, 0} } }, /* 26: */
154 {{{0, 0, 0, 0} } }, /* 27: */
155 {{{0, 0, 0, 0} } }, /* 28: */
156 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
157 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
158 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
159 {{{0} } }, /* 32: PCI */
160 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
161 {1, 0x2110000, 0x2120000, 0x130000},
162 {1, 0x2120000, 0x2122000, 0x124000},
163 {1, 0x2130000, 0x2132000, 0x126000},
164 {1, 0x2140000, 0x2142000, 0x128000},
165 {1, 0x2150000, 0x2152000, 0x12a000},
166 {1, 0x2160000, 0x2170000, 0x110000},
167 {1, 0x2170000, 0x2172000, 0x12e000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000} } },
176 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
177 {{{0} } }, /* 35: */
178 {{{0} } }, /* 36: */
179 {{{0} } }, /* 37: */
180 {{{0} } }, /* 38: */
181 {{{0} } }, /* 39: */
182 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
183 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
184 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
185 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
186 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
187 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
188 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
189 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
190 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
191 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
192 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
193 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
194 {{{0} } }, /* 52: */
195 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
196 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
197 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
198 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
199 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
200 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
201 {{{0} } }, /* 59: I2C0 */
202 {{{0} } }, /* 60: I2C1 */
203 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
204 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
205 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
212 0,
216 0,
239 0,
242 0,
244 0,
247 0,
248 0,
249 0,
250 0,
251 0,
253 0,
264 0,
269 0,
273 0,
275 0,
287 dest = addr & 0xFFFF0000; in qlcnic_read_window_reg()
300 dest = addr & 0xFFFF0000; in qlcnic_write_window_reg()
312 int timeout = 0, err = 0, done = 0; in qlcnic_pcie_sem_lock()
342 return 0; in qlcnic_pcie_sem_lock()
348 int err = 0; in qlcnic_pcie_sem_unlock()
355 int err = 0; in qlcnic_ind_rd()
370 int ret = 0; in qlcnic_ind_wr()
389 i = 0; in qlcnic_send_cmd_descs()
394 tx_ring = &adapter->tx_ring[0]; in qlcnic_send_cmd_descs()
417 pbuf->frag_count = 0; in qlcnic_send_cmd_descs()
433 return 0; in qlcnic_send_cmd_descs()
444 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_sre_macaddr_change()
450 mac_req = (struct qlcnic_mac_req *)&req.words[0]; in qlcnic_82xx_sre_macaddr_change()
471 0, QLCNIC_MAC_DEL); in qlcnic_nic_del_mac()
493 return 0; in qlcnic_nic_add_mac()
512 return 0; in qlcnic_nic_add_mac()
538 0xff, 0xff, 0xff, 0xff, 0xff, 0xff in __qlcnic_set_multi()
580 adapter->drv_mac_learn = 0; in __qlcnic_set_multi()
597 __qlcnic_set_multi(netdev, 0); in qlcnic_set_multi()
605 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_nic_set_promisc()
613 req.words[0] = cpu_to_le64(mode); in qlcnic_82xx_nic_set_promisc()
627 cur->mac_addr, 0, QLCNIC_MAC_DEL); in qlcnic_82xx_free_mac_list()
642 for (i = 0; i < adapter->fhash.fbucket_size; i++) { in qlcnic_prune_lb_filters()
661 for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) { in qlcnic_prune_lb_filters()
686 for (i = 0; i < adapter->fhash.fbucket_size; i++) { in qlcnic_delete_lb_filters()
709 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_set_fw_loopback()
713 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32)); in qlcnic_set_fw_loopback()
715 req.words[0] = cpu_to_le64(flag); in qlcnic_set_fw_loopback()
718 if (rv != 0) in qlcnic_set_fw_loopback()
731 qlcnic_set_fw_loopback(adapter, 0); in qlcnic_82xx_set_lb_mode()
736 return 0; in qlcnic_82xx_set_lb_mode()
744 qlcnic_set_fw_loopback(adapter, 0); in qlcnic_82xx_clear_lb_mode()
753 return 0; in qlcnic_82xx_clear_lb_mode()
769 return 0; in qlcnic_82xx_read_phys_port_id()
777 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_set_rx_coalesce()
784 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32); in qlcnic_82xx_set_rx_coalesce()
791 if (rv != 0) in qlcnic_82xx_set_rx_coalesce()
828 return 0; in qlcnic_82xx_config_hw_lro()
830 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_config_hw_lro()
837 word = 0; in qlcnic_82xx_config_hw_lro()
840 if (adapter->ahw->extra_capability[0] & in qlcnic_82xx_config_hw_lro()
845 req.words[0] = cpu_to_le64(word); in qlcnic_82xx_config_hw_lro()
848 if (rv != 0) in qlcnic_82xx_config_hw_lro()
862 return 0; in qlcnic_config_bridged_mode()
864 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_config_bridged_mode()
872 req.words[0] = cpu_to_le64(enable); in qlcnic_config_bridged_mode()
875 if (rv != 0) in qlcnic_config_bridged_mode()
885 #define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3
888 #define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL
897 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, in qlcnic_82xx_config_rss()
898 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, in qlcnic_82xx_config_rss()
899 0x255b0ec26d5a56daULL in qlcnic_82xx_config_rss()
902 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_config_rss()
910 * bits 3-0: hash_method in qlcnic_82xx_config_rss()
921 word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) | in qlcnic_82xx_config_rss()
922 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) | in qlcnic_82xx_config_rss()
923 ((u64)(enable & 0x1) << 8) | in qlcnic_82xx_config_rss()
928 req.words[0] = cpu_to_le64(word); in qlcnic_82xx_config_rss()
929 for (i = 0; i < 5; i++) in qlcnic_82xx_config_rss()
933 if (rv != 0) in qlcnic_82xx_config_rss()
947 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_config_ipaddr()
953 req.words[0] = cpu_to_le64(cmd); in qlcnic_82xx_config_ipaddr()
958 if (rv != 0) in qlcnic_82xx_config_ipaddr()
960 "could not notify %s IP 0x%x request\n", in qlcnic_82xx_config_ipaddr()
969 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_linkevent_request()
974 req.words[0] = cpu_to_le64(enable | (enable << 8)); in qlcnic_82xx_linkevent_request()
976 if (rv != 0) in qlcnic_82xx_linkevent_request()
990 return 0; in qlcnic_send_lro_cleanup()
992 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_send_lro_cleanup()
1002 if (rv != 0) in qlcnic_send_lro_cleanup()
1011 * @returns 0 on success, negative on failure
1017 int rc = 0; in qlcnic_change_mtu()
1054 adapter->rx_csum = 0; in qlcnic_process_flags()
1091 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0; in qlcnic_set_features()
1094 return 0; in qlcnic_set_features()
1106 return 0; in qlcnic_set_features()
1112 /* Returns < 0 if off is not valid,
1115 * 0 if no window access is needed. 'off' is set to 2M addr
1136 return 0; in qlcnic_pci_get_crb_addr_2M()
1160 if (window == 0) { in qlcnic_pci_set_crbwindow_2M()
1161 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off); in qlcnic_pci_set_crbwindow_2M()
1169 "failed to set CRB window to %d off 0x%lx\n", in qlcnic_pci_set_crbwindow_2M()
1173 return 0; in qlcnic_pci_set_crbwindow_2M()
1185 if (rv == 0) { in qlcnic_82xx_hw_write_wx_2M()
1187 return 0; in qlcnic_82xx_hw_write_wx_2M()
1190 if (rv > 0) { in qlcnic_82xx_hw_write_wx_2M()
1203 "%s: invalid offset: 0x%016lx\n", __func__, off); in qlcnic_82xx_hw_write_wx_2M()
1218 if (rv == 0) in qlcnic_82xx_hw_read_wx_2M()
1221 if (rv > 0) { in qlcnic_82xx_hw_read_wx_2M()
1233 "%s: invalid offset: 0x%016lx\n", __func__, off); in qlcnic_82xx_hw_read_wx_2M()
1263 if (op == 0) /* read */ in qlcnic_pci_mem_access_direct()
1268 /* Set window to 0 */ in qlcnic_pci_mem_access_direct()
1269 writel(0, adapter->ahw->ocm_win_crb); in qlcnic_pci_mem_access_direct()
1273 return 0; in qlcnic_pci_mem_access_direct()
1307 if (off & 0xf) { in qlcnic_set_ms_controls()
1308 ms->wd[0] = QLCNIC_MS_WRTDATA_LO; in qlcnic_set_ms_controls()
1309 ms->rd[0] = QLCNIC_MS_RDDATA_LO; in qlcnic_set_ms_controls()
1317 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO; in qlcnic_set_ms_controls()
1318 ms->rd[0] = QLCNIC_MS_RDDATA_ULO; in qlcnic_set_ms_controls()
1333 int j, ret = 0; in qlcnic_pci_mem_write_2M()
1341 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); in qlcnic_pci_mem_write_2M()
1354 off8 = off & ~0xf; in qlcnic_pci_mem_write_2M()
1359 qlcnic_ind_wr(adapter, ms.hi, 0); in qlcnic_pci_mem_write_2M()
1364 for (j = 0; j < MAX_CTL_CHECK; j++) { in qlcnic_pci_mem_write_2M()
1366 if ((temp & TA_CTL_BUSY) == 0) in qlcnic_pci_mem_write_2M()
1376 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0])); in qlcnic_pci_mem_write_2M()
1379 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff); in qlcnic_pci_mem_write_2M()
1380 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff); in qlcnic_pci_mem_write_2M()
1385 for (j = 0; j < MAX_CTL_CHECK; j++) { in qlcnic_pci_mem_write_2M()
1387 if ((temp & TA_CTL_BUSY) == 0) in qlcnic_pci_mem_write_2M()
1397 ret = 0; in qlcnic_pci_mem_write_2M()
1421 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); in qlcnic_pci_mem_read_2M()
1426 ms.off, data, 0); in qlcnic_pci_mem_read_2M()
1430 off8 = off & ~0xf; in qlcnic_pci_mem_read_2M()
1433 qlcnic_ind_wr(adapter, ms.hi, 0); in qlcnic_pci_mem_read_2M()
1438 for (j = 0; j < MAX_CTL_CHECK; j++) { in qlcnic_pci_mem_read_2M()
1440 if ((temp & TA_CTL_BUSY) == 0) in qlcnic_pci_mem_read_2M()
1455 ret = 0; in qlcnic_pci_mem_read_2M()
1465 int offset, board_type, magic, err = 0; in qlcnic_82xx_get_board_info()
1488 if ((gpio & 0x8000) == 0) in qlcnic_82xx_get_board_info()
1520 return 0; in qlcnic_82xx_get_board_info()
1527 int err = 0; in qlcnic_wol_supported()
1538 return 0; in qlcnic_wol_supported()
1547 memset(&req, 0, sizeof(struct qlcnic_nic_req)); in qlcnic_82xx_config_led()
1553 req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum); in qlcnic_82xx_config_led()
1568 int err = 0; in qlcnic_82xx_get_beacon_state()
1570 if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) { in qlcnic_82xx_get_beacon_state()
1609 int err = 0; in qlcnic_82xx_read_crb()
1639 return qlcnic_pcie_sem_lock(adapter, 5, 0); in qlcnic_82xx_api_lock()
1659 qlcnic_clr_all_drv_state(adapter, 0); in qlcnic_82xx_shutdown()
1666 return 0; in qlcnic_82xx_shutdown()