Lines Matching +full:32 +full:- +full:bits
10 * vxge-reg.h: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O Virtualized
12 * Copyright(c) 2002-2010 Exar Corp.
18 * vxge_mBIT(loc) - set bit at offset
23 * vxge_vBIT(val, loc, sz) - set bits at offset
25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
29 * vxge_bVALn(bits, loc, n) - Get the value of n bits at location
31 #define vxge_bVALn(bits, loc, n) \ argument
32 ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1))
34 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \ argument
35 vxge_bVALn(bits, 0, 16)
36 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \ argument
37 vxge_bVALn(bits, 48, 8)
38 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \ argument
39 vxge_bVALn(bits, 56, 8)
41 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \ argument
42 vxge_bVALn(bits, 3, 5)
43 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \ argument
44 vxge_bVALn(bits, 5, 3)
89 #define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1) argument
91 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \ argument
92 vxge_bVALn(bits, 0, 32)
94 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \ argument
95 vxge_bVALn(bits, 50, 14)
97 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \ argument
98 vxge_bVALn(bits, 0, 17)
100 #define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \ argument
101 vxge_bVALn(bits, 3, 5)
103 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \ argument
104 vxge_bVALn(bits, 17, 15)
122 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits argument
123 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits argument
125 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \ argument
126 vxge_bVALn(bits, 1, 15)
127 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \ argument
128 vxge_bVALn(bits, 17, 15)
129 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \ argument
130 vxge_bVALn(bits, 33, 15)
163 #define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ argument
164 vxge_bVALn(bits, 0, 48)
167 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ argument
168 vxge_bVALn(bits, 0, 48)
172 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \ argument
173 vxge_bVALn(bits, 55, 5)
176 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \ argument
177 vxge_bVALn(bits, 62, 2)
204 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ argument
205 vxge_bVALn(bits, 0, 48)
208 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12) argument
211 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) vxge_bVALn(bits, 0, 11) argument
214 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \ argument
215 vxge_bVALn(bits, 3, 1)
217 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \ argument
218 vxge_bVALn(bits, 7, 1)
220 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \ argument
221 vxge_bVALn(bits, 8, 16)
224 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \ argument
225 vxge_bVALn(bits, 3, 1)
227 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \ argument
228 vxge_bVALn(bits, 4, 4)
231 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \ argument
232 vxge_bVALn(bits, 10, 2)
238 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \ argument
239 vxge_bVALn(bits, 15, 1)
241 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \ argument
242 vxge_bVALn(bits, 19, 1)
244 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \ argument
245 vxge_bVALn(bits, 23, 1)
247 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \ argument
248 vxge_bVALn(bits, 27, 1)
250 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \ argument
251 vxge_bVALn(bits, 31, 1)
253 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \ argument
254 vxge_bVALn(bits, 35, 1)
256 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \ argument
257 vxge_bVALn(bits, 39, 1)
259 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \ argument
260 vxge_bVALn(bits, 43, 1)
263 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \ argument
264 vxge_bVALn(bits, 3, 1)
266 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \ argument
267 vxge_bVALn(bits, 9, 7)
271 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \ argument
272 vxge_bVALn(bits, 0, 8)
275 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \ argument
276 vxge_bVALn(bits, 8, 1)
278 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \ argument
279 vxge_bVALn(bits, 9, 7)
282 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \ argument
283 vxge_bVALn(bits, 16, 8)
286 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \ argument
287 vxge_bVALn(bits, 24, 1)
289 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \ argument
290 vxge_bVALn(bits, 25, 7)
293 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \ argument
294 vxge_bVALn(bits, 0, 8)
297 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \ argument
298 vxge_bVALn(bits, 8, 1)
300 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \ argument
301 vxge_bVALn(bits, 9, 7)
304 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \ argument
305 vxge_bVALn(bits, 16, 8)
308 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \ argument
309 vxge_bVALn(bits, 24, 1)
311 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \ argument
312 vxge_bVALn(bits, 25, 7)
316 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \ argument
317 vxge_bVALn(bits, 0, 32)
319 vxge_vBIT(val, 0, 32)
320 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \ argument
321 vxge_bVALn(bits, 32, 32)
323 vxge_vBIT(val, 32, 32)
325 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \ argument
326 vxge_bVALn(bits, 0, 16)
329 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \ argument
330 vxge_bVALn(bits, 16, 16)
333 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \ argument
334 vxge_bVALn(bits, 32, 4)
336 vxge_vBIT(val, 32, 4)
337 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \ argument
338 vxge_bVALn(bits, 36, 4)
341 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \ argument
342 vxge_bVALn(bits, 40, 2)
345 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \ argument
346 vxge_bVALn(bits, 42, 2)
350 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \ argument
351 vxge_bVALn(bits, 0, 64)
354 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \ argument
355 vxge_bVALn(bits, 3, 1)
358 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \ argument
359 vxge_bVALn(bits, 3, 1)
362 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ argument
363 vxge_bVALn(bits, 0, 48)
369 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \ argument
370 vxge_bVALn(bits, 0, 8)
373 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \ argument
374 vxge_bVALn(bits, 8, 1)
376 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \ argument
377 vxge_bVALn(bits, 9, 7)
380 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \ argument
381 vxge_bVALn(bits, 16, 8)
384 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \ argument
385 vxge_bVALn(bits, 24, 1)
387 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \ argument
388 vxge_bVALn(bits, 25, 7)
391 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \ argument
392 vxge_bVALn(bits, 32, 8)
394 vxge_vBIT(val, 32, 8)
395 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \ argument
396 vxge_bVALn(bits, 40, 1)
398 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \ argument
399 vxge_bVALn(bits, 41, 7)
402 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \ argument
403 vxge_bVALn(bits, 48, 8)
406 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \ argument
407 vxge_bVALn(bits, 56, 1)
409 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \ argument
410 vxge_bVALn(bits, 57, 7)
426 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \ argument
427 vxge_bVALn(bits, 0, 8)
429 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \ argument
430 vxge_bVALn(bits, 8, 8)
432 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \ argument
433 vxge_bVALn(bits, 16, 16)
437 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \ argument
438 vxge_bVALn(bits, 32, 8)
439 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8)
440 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \ argument
441 vxge_bVALn(bits, 40, 8)
443 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \ argument
444 vxge_bVALn(bits, 48, 16)
447 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \ argument
448 vxge_bVALn(bits, 0, 8)
450 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \ argument
451 vxge_bVALn(bits, 8, 8)
453 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \ argument
454 vxge_bVALn(bits, 16, 16)
458 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \ argument
459 vxge_bVALn(bits, 32, 8)
460 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8)
461 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \ argument
462 vxge_bVALn(bits, 40, 8)
464 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ argument
465 vxge_bVALn(bits, 48, 16)
467 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) vxge_bVALn(bits, 0, 8) argument
469 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ argument
470 vxge_bVALn(bits, 0, 18)
472 #define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \ argument
473 vxge_bVALn(bits, 48, 16)
474 #define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \ argument
475 vxge_bVALn(bits, 32, 32)
476 #define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits) vxge_bVALn(bits, 48, 16) argument
477 #define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \ argument
478 vxge_bVALn(bits, 0, 32)
479 #define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \ argument
480 vxge_bVALn(bits, 0, 32)
481 #define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \ argument
482 vxge_bVALn(bits, 0, 32)
483 #define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits) argument
484 #define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits) argument
485 #define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \ argument
486 vxge_bVALn(bits, 32, 32)
487 #define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \ argument
488 vxge_bVALn(bits, 32, 32)
489 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \ argument
490 vxge_bVALn(bits, 0, 32)
491 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \ argument
492 vxge_bVALn(bits, 32, 32)
493 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \ argument
494 vxge_bVALn(bits, 0, 32)
495 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \ argument
496 vxge_bVALn(bits, 32, 32)
497 #define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \ argument
498 vxge_bVALn(bits, 0, 32)
499 #define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \ argument
500 vxge_bVALn(bits, 32, 32)
501 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\ argument
502 ) vxge_bVALn(bits, 48, 16)
503 #define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16) argument
504 #define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \ argument
505 vxge_bVALn(bits, 16, 16)
506 #define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \ argument
507 vxge_bVALn(bits, 32, 16)
508 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) vxge_bVALn(bits, 0, 16) argument
509 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \ argument
510 vxge_bVALn(bits, 16, 16)
511 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \ argument
512 vxge_bVALn(bits, 32, 16)
514 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \ argument
515 vxge_bVALn(bits, 0, 32)
516 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \ argument
517 vxge_bVALn(bits, 32, 32)
518 #define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\ argument
519 ) vxge_bVALn(bits, 32, 32)
520 #define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\ argument
521 ) vxge_bVALn(bits, 32, 32)
523 VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \ argument
524 vxge_bVALn(bits, 32, 32)
525 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \ argument
526 vxge_bVALn(bits, 0, 32)
527 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \ argument
528 vxge_bVALn(bits, 32, 32)
529 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \ argument
530 vxge_bVALn(bits, 0, 32)
531 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \ argument
532 vxge_bVALn(bits, 32, 32)
533 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \ argument
534 vxge_bVALn(bits, 0, 32)
535 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \ argument
536 vxge_bVALn(bits, 32, 32)
537 #define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \ argument
538 vxge_bVALn(bits, 32, 32)
539 #define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \ argument
540 vxge_bVALn(bits, 32, 32)
542 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits) vxge_bVALn(bits, 0, 32) argument
543 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits) vxge_bVALn(bits, 32, 32) argument
544 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) vxge_bVALn(bits, 0, 32) argument
545 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) vxge_bVALn(bits, 32, 32) argument
546 #define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) vxge_bVALn(bits, 0, 32) argument
547 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) vxge_bVALn(bits, 0, 16) argument
548 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) vxge_bVALn(bits, 16, 16) argument
549 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16) argument
550 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) vxge_bVALn(bits, 0, 16) argument
551 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL(bits, 16, 16) argument
552 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16) argument
554 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \ argument
555 vxge_bVALn(bits, 32, 32)
557 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \ argument
558 vxge_bVALn(bits, 0, 8)
559 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \ argument
560 vxge_bVALn(bits, 8, 8)
561 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \ argument
562 vxge_bVALn(bits, 16, 8)
564 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \ argument
565 vxge_bVALn(bits, 0, 8)
566 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \ argument
567 vxge_bVALn(bits, 8, 8)
568 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \ argument
569 vxge_bVALn(bits, 16, 8)
591 * The registers are memory mapped and are native big-endian byte order. The
592 * little-endian hosts are handled by enabling hardware byte-swapping for
626 u8 unused001e0[0x001e0-0x000e8];
632 u8 unused00278[0x00278-0x00270];
636 u8 unused00390[0x00390-0x00300];
640 u8 unused004a0[0x004a0-0x00418];
679 u8 unused00b00[0x00b00-0x00a48];
685 u8 unused00b80[0x00b80-0x00b10];
699 u8 unused00c00[0x00c00-0x00bb0];
711 u8 unused00d00[0x00d00-0x00c28];
723 u8 unused00d40[0x00d40-0x00d28];
729 u8 unused00da8[0x00da8-0x00d50];
760 u8 unused00e70[0x00e70-0x00e68];
765 u8 unused00e80[0x00e80-0x00e78];
803 u8 unused00ed0[0x00ed0-0x00ec0];
813 u8 unused00fc0[0x00fc0-0x00ef0];
817 u8 unused01080[0x01080-0x00fc8];
821 u8 unused010c0[0x010c0-0x01088];
825 u8 unused01100[0x01100-0x010c8];
837 u8 unused01128[0x01128-0x01120];
847 u8 unused01200[0x01200-0x01138];
904 u8 unused00a00[0x00a00-0x00028];
1030 u8 unused00be8[0x00be8-0x00b60];
1402 u8 unused00cc8[0x00cc8-0x00cb0];
1420 #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32)
1424 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW vxge_mBIT(32)
1452 u8 unused00e00[0x00e00-0x00d08];
1462 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32)
1469 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32)
1471 u8 unused00e40[0x00e40-0x00e28];
1517 u8 unused0f28[0x0f28-0x0e90];
1531 u8 unused0fc8[0x0fc8-0x0f30];
1543 u8 unused1068[0x01068-0x0fd0];
1561 u8 unused1100[0x01100-0x1080];
1566 u8 unused1600[0x01600-0x1108];
1574 u8 unused01618[0x01618-0x01610];
1600 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR vxge_mBIT(32)
1635 u8 unused016c0[0x016c0-0x01678];
1647 u8 unused016e0[0x016e0-0x016c8];
1658 u8 unused01710[0x01710-0x016f8];
1673 u8 unused01758[0x01758-0x01740];
1690 u8 unused017d0[0x017d0-0x017b8];
1694 u8 unused01800[0x01800-0x017e8];
1718 u8 unused01828[0x01828-0x01810];
1748 u8 unused01890[0x01890-0x01850];
1750 u8 unused01968[0x01968-0x01898];
1757 u8 unused01a00[0x01a00-0x01970];
1768 u8 unused01e00[0x01e00-0x01a88];
1864 u8 unused01f40[0x01f40-0x01ed0];
1871 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4)
1877 #define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16)
1886 #define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8)
1889 u8 unused01f80[0x01f80-0x01f68];
1906 u8 unused02020[0x02020-0x01fc0];
1925 vxge_vBIT(val, 32, 16)
1926 u8 unused02040[0x02040-0x02038];
1936 #define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16)
1941 #define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16)
1949 u8 unused02070[0x02070-0x02068];
1975 u8 unused020f0[0x020f0-0x020e8];
1985 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16)
2002 vxge_vBIT(val, 32, 16)
2037 vxge_vBIT(val, 32, 16)
2061 vxge_mBIT(32)
2083 vxge_vBIT(val, 32, 8)
2090 u8 unused02208[0x02700-0x021d0];
2122 u8 unused027a8[0x027a8-0x02770];
2145 u8 unused02900[0x02900-0x027d0];
2159 u8 unused03000[0x03000-0x02928];
2186 u8 unused03100[0x03100-0x03040];
2193 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8)
2197 u8 unused033b8[0x033b8-0x03108];
2201 u8 unused03400[0x03400-0x033c0];
2276 u8 unused03600[0x03600-0x03470];
2289 u8 unused03a00[0x03a00-0x03610];
2297 u8 unused04000[0x04000-0x03a10];
2312 u8 unused04818[0x04818-0x04010];
2319 #define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16)
2334 u8 unused04900[0x04900-0x048d0];
2347 #define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
2350 u8 unused04b00[0x04b00-0x04a28];
2388 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR vxge_mBIT(32)
2405 u8 unused04f00[0x04f00-0x04b58];
2444 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR vxge_mBIT(32)
2482 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2)
2506 u8 unused04fe8[0x04f50-0x04f40];
2515 #define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32)
2516 u8 unused05200[0x05200-0x04f70];
2597 u8 unused05340[0x05340-0x05240];
2609 #define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32)
2610 #define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32)
2611 u8 unused05368[0x05380-0x05360];
2671 vxge_mBIT(32)
2699 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 vxge_mBIT(32)
2721 u8 unused05600[0x05600-0x053b0];
2756 u8 unused05658[0x05658-0x05630];
2761 u8 unused05668[0x05668-0x05660];
2765 vxge_vBIT(val, 32, 32)
2766 u8 unused056c0[0x056c0-0x05670];
2771 u8 unused05800[0x05800-0x056c8];
2811 u8 unused05868[0x05870-0x05860];
2818 u8 unused05898[0x05898-0x05880];
2822 vxge_vBIT(val, 32, 32)
2823 u8 unused05900[0x05900-0x058a0];
2847 u8 unused05978[0x05978-0x05940];
2854 u8 unused059a0[0x059a0-0x05980];
2872 u8 unused05a20[0x05a20-0x05a00];
2881 vxge_vBIT(val, 32, 16)
2895 u8 unused05d48[0x05d48-0x05a40];
2901 u8 unused06420[0x06420-0x05dd0];
2909 #define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32)
2910 #define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32)
2912 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32)
2913 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32)
2915 #define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32)
2919 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16)
2923 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16)
2925 u8 unused07000[0x07000-0x06658];
2985 vxge_mBIT(32)
3027 u8 unused07028[0x07028-0x07020];
3072 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_FSM_ERR vxge_mBIT(32)
3121 u8 unused07090[0x07090-0x07088];
3137 u8 unused070b0[0x070b0-0x070a8];
3156 u8 unused070d0[0x070d0-0x070c8];
3174 u8 unused07128[0x07128-0x07118];
3195 u8 unused072f0[0x072f0-0x072c0];
3202 u8 unused07378[0x07378-0x07300];
3229 u8 unused07500[0x07500-0x074a0];
3266 u8 unused07950[0x07950-0x07520];
3278 u8 unused07be8[0x07be8-0x07958];
3285 u8 unused07d30[0x07d30-0x07bf8];
3288 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32)
3289 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32)
3292 vxge_vBIT(val, 32, 32)
3295 vxge_vBIT(val, 32, 32)
3298 vxge_vBIT(val, 32, 32)
3300 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32)
3302 vxge_vBIT(val, 32, 32)
3304 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32)
3305 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32)
3307 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32)
3308 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32)
3310 #define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32)
3312 #define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32)
3314 u8 unused07f08[0x07f08-0x07ef8];
3324 u8 unused08000[0x08000-0x07f40];
3334 u8 unused09000[0x09000-0x8010];
3348 u8 unused09400[0x09400-0x09028];
3362 u8 unused09800[0x09800-0x09428];
3375 u8 unused09b00[0x09b00-0x09828];
3380 u8 unused09c30[0x09c30-0x09b88];
3387 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4)
3401 vxge_vBIT(val, 32, 16)
3414 vxge_vBIT(val, 32, 4)
3419 u8 unused09c90[0x09c90-0x09c80];
3423 u8 unused09d40[0x09d40-0x09ca0];
3426 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32)
3427 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32)
3438 u8 unused09d80[0x09d80-0x09d70];
3473 #define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32)
3474 u8 unused09de0[0x09de0-0x09dd0];
3513 vxge_mBIT(32)
3538 vxge_vBIT(val, 32, 32)
3539 u8 unused09e30[0x09e30-0x09e20];
3582 vxge_vBIT(val, 32, 16)
3588 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16)
3593 u8 unused0a200[0x0a200-0x09e80];
3596 u8 unused0a400[0x0a400-0x0a288];
3603 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8)
3605 u8 unused0ac90[0x0ac90-0x0a488];
3613 vxge_vBIT(val, 0, 32)
3614 u8 unused00100[0x00100-0x00008];
3646 u8 unused00160[0x00160-0x00140];
3662 u8 unused00200[0x00200-0x00188];
3668 u8 unused00210[0x00210-0x00208];
3674 u8 unused00220[0x00220-0x00218];
3696 u8 unused00280[0x00280-0x00278];
3710 u8 unused002a8[0x002a8-0x00298];
3727 u8 unused00880[0x00880-0x002e0];
3740 u8 unused008c0[0x008c0-0x008a8];
3745 u8 unused00900[0x00900-0x008c8];
3781 u8 unused00040[0x00040-0x00000];
3794 u8 unused00100[0x00100-0x00060];
3797 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
3798 u8 unused00140[0x00140-0x00108];
3803 u8 unused001c0[0x001c0-0x00148];
3886 u8 unused00240[0x00240-0x00208];
3890 u8 unused00260[0x00260-0x00248];
3912 vxge_vBIT(val, 32, 4)
3920 vxge_vBIT(val, 32, 16)
3933 u8 unused002c0[0x002c0-0x002a8];
3941 u8 unused00300[0x00300-0x002e0];
3944 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32)
3950 u8 unused00360[0x00360-0x00318];
3965 u8 unused00380[0x00380-0x00370];
3984 #define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32)
3985 u8 unused00a00[0x00a00-0x00308];
3990 u8 unused00a30[0x00a30-0x00a10];
4007 u8 unused00a60[0x00a60-0x00a50];
4015 #define VXGE_HW_PRC_CFG4_IGNORE_OWNERSHIP vxge_mBIT(32)
4052 vxge_vBIT(val, 32, 32)
4055 u8 unused00c00[0x00c00-0x00ac0];
4072 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
4084 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
4095 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
4111 u8 unused00c60[0x00c60-0x00c50];
4124 u8 unused00c80[0x00c80-0x00c78];
4157 u8 unused00d00[0x00d00-0x00cb0];
4165 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8)
4172 u8 unused00d30[0x00d30-0x00d28];
4190 u8 unused00d80[0x00d80-0x00d58];
4220 u8 unused01000[0x01000-0x00da0];
4235 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16)
4241 #define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6)
4244 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32)
4251 #define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32)
4252 #define VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN vxge_mBIT(32)
4262 #define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
4268 u8 unused01100[0x01100-0x01090];
4303 #define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32)
4306 vxge_vBIT(val, 0, 32)
4308 vxge_vBIT(val, 32, 32)
4310 #define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32)
4313 u8 unused01180[0x01180-0x01138];
4339 #define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
4352 #define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32)
4356 #define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
4364 u8 unused01380[0x01380-0x01208];
4371 u8 unused01400[0x01400-0x01388];
4376 u8 unused01480[0x01480-0x01408];
4382 u8 unused014d0[0x014d0-0x01488];
4387 #define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16)
4393 vxge_vBIT(val, 32, 32)
4394 u8 unused014f0[0x014f0-0x014e0];
4398 u8 unused01e00[0x01e00-0x014f8];
4407 u8 unused01e20[0x01e20-0x01e10];
4414 u8 unused01ea0[0x01ea0-0x01e38];
4422 u8 unused02000[0x02000-0x01eb0];
4460 u8 unused02040[0x02040-0x02038];
4488 u8 unused02108[0x02108-0x020a0];
4495 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8)
4506 u8 unused02158[0x02158-0x02130];
4510 u8 unused02200[0x02200-0x02160];
4526 u8 unused02220[0x02220-0x02218];
4560 u8 unused02268[0x02268-0x02228];
4570 u8 unused02280[0x02280-0x02278];
4582 u8 unused022b0[0x022b0-0x022a8];
4591 #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32)
4592 u8 unused02300[0x02300-0x022c8];
4595 #define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32)
4597 #define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32)
4599 #define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32)
4607 #define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32)
4609 #define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32)
4612 vxge_vBIT(val, 0, 32)
4614 vxge_vBIT(val, 32, 32)
4617 vxge_vBIT(val, 0, 32)
4619 vxge_vBIT(val, 32, 32)
4622 vxge_vBIT(val, 32, 32)
4625 vxge_vBIT(val, 32, 32)
4626 u8 unused02648[0x02648-0x02358];